Strained CMOS FinFET Transistor Strain Engineering
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Solution Overview
Problem
Current semiconductor technologies face challenges in integrating n-type and p-type field effect transistors on the same chip with effective strain engineering, as global biaxial tensile strain enhances n-channel performance but deteriorates p-channel performance, and existing methods become less effective as transistor pitch scales down.
Innovation Solution
The method involves forming long and short fins in a strained semiconductor layer, where n-type transistors are fabricated on long fins to maintain uniaxial tensile strain and p-type transistors on short fins to relax strain, allowing for enhanced performance of both transistor types on the same substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If local strain engineering is used to exert uniaxial tensile and compressive strain on n-channel and p-channel MOSFETs, then transistor performance is improved, but effectiveness decreases as transistor pitch scales down
Solution Approach 1:
The patent transitions from uniaxial strain (one-dimensional) to biaxial tensile strain (two-dimensional) for the n-channel region. This dimensional change allows strain to be applied in both in-plane directions simultaneously, providing more comprehensive strain engagement that remains effective even as transistor pitch scales down to smaller dimensions
2Speed
If dual stress liner method is used to deposit nitride layers with opposite strains on n- and p-channel transistors, then strain is applied to both transistor types, but process complexity increases significantly
Solution Approach 1:
The patent extracts the strain control function from a complex dual-layer nitride system and simplifies it to a single strained semiconductor layer with spatially differentiated regions. By removing the dual stress liner structure and replacing it with region-based strain management, the patent maintains strain benefits for both transistor types while dramatically reducing process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved performance for both n-type and p-type transistors by maintaining uniaxial tensile strain in n-type transistors and relaxing strain in p-type transistors, potentially doubling n-type transistor performance and extending the effectiveness of strain engineering to future technology nodes.
Implementation Method 1
Strained silicon is being used by the semiconductor industry to improve transistor performance. Increased strain levels are desired in future technology nodes
Implementation Method 2
it is desired that the biaxial strain is converted to uniaxial strain by preferential relaxation of the strain. Electron mobility enhancement up to 100% is achieved if biaxial tensile strain in SSDOI is converted into uniaxial strain
Data Source
AI summary
A semiconductor device and fabrication method include a strained semiconductor layer having a strain in one axis. A long fin and a short fin are formed in the semiconductor layer such that the long fin has a strained length along the one axis. An n-type transistor is formed on the long fin, and a p-type transistor is formed on the at least one short fin. The strain in the n-type transistor improves performance.