Strained CMOS Source/Drain Integration via Segmented SiGe and C-Si
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Solution Overview
Problem
Current semiconductor device fabrication methods face limitations in improving electron and hole mobility, particularly as devices shrink in size, and existing strain-inducing techniques may not be sufficient for next-generation devices.
Innovation Solution
The method involves forming recessed epitaxial silicon germanium regions in PMOS devices and recessed epitaxial carbon doped silicon regions in NMOS devices within a CMOS device flow, with the carbon doped silicon regions being formed after significant thermal anneal processes to prevent degradation, and both types of regions are used to induce strain and enhance carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single type of strain-inducing layer is formed over the gate structure, then the manufacturing process is simple, but the channel mobility improvement is insufficient for next-generation devices
Solution Approach 1:
The patent divides the strain-inducing structure into two separate segments: silicon germanium regions formed in recesses on one side of the gate, and carbon doped silicon regions formed in recesses on the other side. This segmentation allows each material to be optimized for its specific function (compressive strain for PMOS, tensile strain for NMOS) while maintaining process simplicity through sequential formation.
Solution Approach 2:
The patent applies different material compositions and strain types to different locations: silicon germanium provides compressive strain for PMOS devices, while carbon doped silicon provides tensile strain for NMOS devices. This local quality approach optimizes carrier mobility for each device type according to its specific electrical characteristics.
2Ease of manufacture
If carbon doped silicon regions are formed before thermal anneal processes, then the manufacturing sequence is simplified, but the carbon doped silicon regions degrade during annealing
Solution Approach 1:
The patent performs all significant thermal anneal processes before forming the carbon doped silicon regions. This preliminary action sequence prevents the carbon doped silicon from degrading during high-temperature processing, ensuring material integrity while maintaining a streamlined manufacturing sequence.
Solution Approach 2:
The patent inverts the conventional manufacturing sequence by forming carbon doped silicon regions after thermal annealing instead of before. This reversal protects the carbon-doped material from thermal degradation while achieving the desired strain effects.
3Productivity
If device size is reduced to continue scaling, then device density increases, but channel mobility deteriorates due to smaller channel region
Solution Approach 1:
The patent changes the physical and chemical parameters of the source/drain regions by forming recesses and filling them with strain-inducing materials (silicon germanium and carbon doped silicon). This parameter change introduces mechanical strain that compensates for the mobility loss caused by channel shrinkage, enabling continued device scaling.
Solution Approach 2:
The patent uses composite material structures: silicon germanium combined with silicon substrate for PMOS, and carbon doped silicon combined with silicon substrate for NMOS. These composite structures create lattice mismatch that induces strain in the channel, improving carrier mobility despite reduced channel dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves channel mobility in both PMOS and NMOS devices by inducing mechanical stress through lattice mismatch, enhancing transistor performance and scalability.
Implementation Method 1
inducing strain and enhancing carrier mobility through lattice mismatch
Implementation Method 2
annealing the first source/drain regions and second source/drain regions to form activated first source/drain regions and activated second source/drain regions
Data Source
AI summary
The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes providing a substrate (210) having a PMOS device region (220) and NMOS device region (260). Thereafter, a first gate structure (240) and a second gate structure (280) are formed over the PMOS device region and the NMOS device region, respectively. Additionally, recessed epitaxial SiGe regions (710) may be formed in the substrate on opposing sides of the first gate structure. Moreover, first source/drain regions may be formed on opposing sides of the first gate structure and second source/drain regions on opposing sides of the second gate structure. The first source/drain regions and second source/drain regions may then be annealed to form activated first source/drain regions (1110) and activated second source/drain regions (1120), respectively. Additionally, recessed epitaxial carbon doped silicon regions (1410) may be formed in the substrate on opposing sides of the second gate structure after annealing.