Strained CMOS Transistor Fabrication via Stress Memorization
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Solution Overview
Problem
Conventional methods for enhancing carrier mobility in CMOS transistors, such as forming mechanical stresses within the channel region, are no longer sufficient as semiconductor devices become more integrated and demand for high-speed performance increases.
Innovation Solution
A method involving amorphizing processes in source/drain regions, followed by stressor deposition and annealing to form strained silicon channels, utilizing stress memorization technique (SMT) and solid-phase epitaxy (SPE) to enhance carrier mobility by creating tensile and compressive stresses in N-type and P-type transistors, respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional mechanical stress methods are used to enhance carrier mobility, then carrier mobility is improved, but the method is no longer sufficient for high-speed CMOS as device integration increases
Solution Approach 1:
The patent changes the physical state of the source/drain region from crystalline to amorphous through ion implantation, then uses thermal annealing to restore crystallinity while preserving stress. This parameter change in material structure enables more effective stress transfer to the channel region, achieving higher carrier mobility and meeting high-speed CMOS requirements
Solution Approach 2:
The patent creates a composite structure by combining amorphous source/drain regions with crystalline channel regions. The amorphous source/drain regions provide enhanced stress control, while the crystalline channel maintains high carrier mobility. This composite approach overcomes the limitations of conventional homogeneous structures
2Reliability
If SiGe layer is epitaxially grown to form compressive strained channel, then hole mobility is enhanced, but the method cannot provide both tensile and compressive stress for CMOS
Solution Approach 1:
The patent applies different stress conditions to different transistor types within the CMOS device. N-type transistors receive tensile stress while P-type transistors receive compressive stress through selective amorphization and annealing processes. This local differentiation enables optimal carrier mobility for both transistor types without requiring separate device structures
Solution Approach 2:
Instead of using different materials (SiGe for compression) to achieve different stress types, the patent inverts the approach by using the same crystalline-amorphous-crystalline process sequence but controlling the annealing conditions and stressor application to produce opposite stress directions in different transistor regions
3Reliability
If amorphizing process is performed in source/drain region followed by annealing, then strained silicon channel is formed with enhanced carrier mobility, but the process complexity increases
Solution Approach 1:
The patent performs the amorphizing process and stressor deposition in advance, before final device completion. The stressors are deposited and annealing is performed early in the process flow, allowing subsequent steps to build upon the already-established stress patterns without requiring additional stress-related processing
Solution Approach 2:
The patent merges multiple functions into the annealing step: it simultaneously recovers the crystalline structure of the amorphized source/drain regions, transfers stress to the channel region, and forms the final strained silicon channel. This consolidation reduces the total number of process steps compared to separate operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly enhances carrier mobility in CMOS transistors, improving their performance by forming strained silicon channels through stress memorization and solid-phase epitaxy techniques, addressing the limitations of existing stress-based enhancement methods.
Implementation Method 1
performing a first amorphizing process in the first source/drain region
Implementation Method 2
performing a first annealing process to form a first strained silicon channel in the substrate under the first gate
Implementation Method 3
performing a first annealing process to form a first strained silicon channel
Implementation Method 4
forming mechanical stresses within the channel region... a compressive strained channel can be formed
Data Source
AI summary
A method of fabricating a CMOS transistor includes forming strained channels by re-crystallized amorphous polysilicon with the tensile film or the compressive film during annealing. C or Ge ions are optionally used to form solid-phase epitaxy to amplify the stress in the strained channel. Therefore, the charge carrier mobility in a CMOS transistor is improved.