Strained Dielectric Layer for FET Channel Stress and Short Channel Effect Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for introducing stress into field effect transistors to suppress short channel effects and enhance carrier mobility are inadequate, leading to increased threshold voltage, parasitic resistance, and decreased channel carrier mobility, especially as devices downscale to sub-100 nm regimes.
Innovation Solution
A strained dielectric layer is interposed between the source/drain region and the substrate of a field effect transistor to induce strain in the channel, improving carrier mobility and suppressing short channel effects, with the dielectric layer's stress properties modulated to suit specific device types and performance needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional stress introduction methods (Si/SiGe heterojunction, heterojunction source/drain, covering strained layer) are used, then carrier mobility is improved, but short channel effect suppression capability is not substantially improved and device structure remains unchanged
Solution Approach 1:
A relaxed dielectric layer is introduced as an intermediary between the substrate and source/drain regions. This dielectric layer serves as a mediator that transmits stress to the channel while simultaneously providing structural isolation that suppresses short channel effects. The dielectric layer acts as a buffer that decouples the stress introduction function from the structural support function, allowing independent optimization of both capabilities.
Solution Approach 2:
The relaxed dielectric layer performs multiple functions simultaneously: it introduces stress to improve carrier mobility, suppresses short channel effects through structural isolation, and maintains device structural integrity. This multi-functional element replaces the need for separate stress introduction structures and short channel effect mitigation structures, achieving both goals through a single integrated solution.
2Reliability
If substrate doping concentration is increased to suppress short channel effect, then short channel effect is suppressed, but threshold voltage increases and on-state current decreases
Solution Approach 1:
The relaxed dielectric layer acts as an intermediary that provides short channel effect suppression through structural isolation without requiring increased substrate doping. By physically separating the source/drain regions from direct contact with the substrate, the dielectric layer prevents carrier diffusion and punch-through effects that cause short channel problems, thereby maintaining low threshold voltage and high on-state current.
3Productivity
If device dimensions are downscaled to sub-100 nm regime, then device integration density is improved, but short channel effect deterioration makes further scaling difficult
Solution Approach 1:
The relaxed dielectric layer serves as a critical intermediary structure that enables continued device downscaling to sub-100 nm regime. By providing structural isolation and stress transmission in a compact configuration, the dielectric layer allows further scaling without the short channel effect deterioration that plagues conventional structures, thereby maintaining both high integration density and reliable device operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively enhances electron and hole mobility while fundamentally improving the device structure, allowing for better suppression of short channel effects and facilitating device downscaling, outperforming conventional stress introduction methods.
Implementation Method 1
a stress is introduced in a channel region of a transistor by means of a structure, a material and a process design of the device, so that a lattice structure of the channel portion of the substrate is changed, thereby a mobility of carriers in the channel is increased
Data Source
AI summary
The present invention relates to CMOS ultra large scale integrated circuits, and provides a method for introducing channel stress and a field effect transistor fabricated by the same. According to the present invention, a strained dielectric layer is interposed between source/drain regions and a substrate of a field effect transistor, and a strain is induced in a channel by the strained dielectric layer which directly contacts the substrate, so as to improve a carrier mobility of the channel and a performance of the device. The specific effects of the invention include: a tensile strain may be induced in the channel by using the strained dielectric layer having a tensile strain in order to increase an electron mobility of the channel; a compressive strain may be induced in the channel by using the strained dielectric layer having a compressive strain in order to increase a hole mobility of the channel. According to the invention, not only an effectiveness of the introduction of channel stress is ensued, but the device structure of the field effect transistor is also improved fundamentally, so that a capability for suppressing a short channel effect of the device is increased.