Strained Epitaxial Transistor Channels via Interlayered Stressors
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Solution Overview
Problem
As transistors are miniaturized, maintaining stress in the channel region becomes increasingly difficult, as the source and drain region volume shrinks, and existing methods rely on these regions to supply stress, which limits transistor performance.
Innovation Solution
The use of epitaxial interlayered structures with alternating compressive and tensile strains, grown on a substrate, to impart stress directly into the channel region, allowing for taller strained channel structures without strain relaxation, thereby maintaining performance without relying on source and drain stressors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are miniaturized to increase integration density, then productivity and integration density improve, but the source and drain region volume shrinks, making it difficult to maintain stress in the channel region
Solution Approach 1:
The patent introduces a stressor layer as an intermediary element between the substrate and the channel region. This stressor layer, composed of materials with different lattice constants (e.g., SiGe for compressive stress or SiC for tensile stress), acts as a mediator to impart stress directly to the channel region without relying on the shrinking source and drain regions. The stressor layer is grown epitaxially on the substrate and positioned to contact or be adjacent to the channel, thereby resolving the contradiction by providing a dedicated stress delivery mechanism independent of the miniaturized source/drain structures.
Solution Approach 2:
The patent transitions from relying on in-plane stress delivery through source and drain regions to using a vertically stacked stressor layer configuration. By growing the stressor layer in the vertical dimension on the substrate and positioning it beneath or adjacent to the channel region, the patent creates a new dimensional approach to stress delivery. This vertical stacking allows stress to be imparted through the thickness of the channel rather than through lateral expansion, enabling stress maintenance even as the channel dimensions are reduced for higher integration density.
2Reliability
If source and drain regions are used to supply stress to the channel, then stress is imparted to improve transistor performance, but the source and drain volume must be increased, which complicates further miniaturization
Solution Approach 1:
The patent replaces the source and drain regions as stress suppliers with a dedicated stressor layer. This stressor layer serves as an intermediary that specifically functions to deliver stress to the channel region without the need to increase source and drain dimensions. The stressor layer is composed of materials engineered to provide the desired stress type (compressive or tensile) through lattice mismatch, thereby decoupling the stress delivery function from the source and drain regions and enabling independent miniaturization of those regions.
Solution Approach 2:
The patent segments the stress delivery function from the source and drain regions by introducing a separate stressor layer. Instead of relying on the source and drain regions to perform both carrier transport and stress delivery, the patent divides these functions: the source and drain regions focus on carrier transport while the stressor layer专门 handles stress delivery. This segmentation allows each component to be optimized independently, enabling further miniaturization of the source and drain regions without compromising stress delivery to the channel.
3Reliability
If taller channel structures are used to maintain performance, then transistor performance is improved, but strain relaxation occurs more easily, limiting the achievable height
Solution Approach 1:
The patent employs composite material structures in the form of alternating layers with different lattice constants (e.g., Si/SiGe or Si/SiC superlattices). These composite structures are grown epitaxially to create a pattern of compressive and tensile layers that collectively provide net stress to the channel region. The alternating composition allows the structure to maintain strain stability at greater heights because the alternating compressive and tensile layers balance each other, preventing the cumulative strain that would lead to relaxation in a single-material structure. This composite approach enables taller channel structures while maintaining the necessary strain for high-performance transistor operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the preservation of strain in channel structures to greater heights than conventional methods, enhancing transistor performance while avoiding the need for source/drain stressors, thus supporting the development of smaller, more integrated semiconductor devices.
Implementation Method 1
The use of epitaxial interlayered structures with alternating compressive and tensile strains, grown on a substrate, to impart stress directly into the channel region
Data Source
AI summary
Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.