Strained Nanosheet FET Structure for Leakage and Capacitance Isolation
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Solution Overview
Problem
In advanced semiconductor technology nodes, dimension scaling poses difficulties in forming contacts and vias to the gate, source, and drain electrodes of field-effect transistors, particularly due to increased complexity and parasitic leakage currents.
Innovation Solution
A dual flexible bottom insulator (FBI) structure is implemented in nanostructure transistors, which prevents parasitic transistor leakage current and reduces parasitic capacitance, while using germanium-containing epitaxial layers to induce tensile stress on silicon nanosheets, enhancing carrier mobility. This structure eliminates Si substrate to Ge lattice mismatch and employs sidewall deposition of compressive stressor films.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dimension scaling is pursued to increase functional density, then production efficiency improves and costs decrease, but parasitic leakage currents increase and manufacturing complexity increases
Solution Approach 1:
A bottom isolation structure comprising a first bottom isolation layer and a second bottom isolation layer is introduced as an intermediary between the source/drain regions and the substrate. This dual-layer isolation structure effectively blocks parasitic leakage currents that would otherwise flow through the substrate, thereby resolving the harmful effect of parasitic leakage while maintaining the benefits of dimension scaling for increased functional density and production efficiency.
2Productivity
If dimension scaling is pursued to increase functional density, then production efficiency improves and costs decrease, but manufacturing complexity increases
Solution Approach 1:
The bottom isolation structure is segmented into two distinct layers: a first bottom isolation layer and a second bottom isolation layer. Each layer can be formed with different materials and properties optimized for specific functions. This segmentation allows for better control of parasitic effects while maintaining compatibility with existing manufacturing processes, thus managing manufacturing complexity effectively.
Solution Approach 2:
The bottom isolation structure serves multiple functions simultaneously: it provides electrical isolation to block parasitic leakage currents, mechanical support for the overlying structures, and stress control for the channel regions. By integrating these multiple functions into a single structural element, the design reduces overall device complexity while maintaining high production efficiency.
3Reliability
If germanium-containing epitaxial layers are used to induce tensile stress on silicon nanosheets, then carrier mobility increases, but lattice mismatch between Si substrate and Ge layers occurs
Solution Approach 1:
The bottom isolation layers act as intermediary structures between the silicon substrate and the germanium-containing epitaxial layers. These isolation layers provide a transition zone that helps accommodate the lattice mismatch between silicon and germanium, reducing dislocation formation while still allowing the germanium layers to induce the desired tensile stress in the silicon nanosheet channels for enhanced carrier mobility.
Solution Approach 2:
The composition and thickness parameters of the bottom isolation layers are carefully optimized to balance two competing requirements: providing sufficient isolation to block parasitic currents and managing lattice mismatch to maintain structural stability. By adjusting these parameters, the system achieves both high carrier mobility through tensile stress and stable composition despite the Si-Ge lattice mismatch.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual FBI structure improves device performance by reducing effective capacitance and increasing carrier mobility in N-type channels, enabling efficient fabrication and operation of nanostructure transistors with enhanced scaling capabilities.
Implementation Method 1
This structure eliminates Si substrate to Ge lattice mismatch
Implementation Method 2
using germanium-containing epitaxial layers to induce tensile stress on silicon nanosheets, enhancing carrier mobility
Implementation Method 3
A dual flexible bottom insulator (FBI) structure is implemented in nanostructure transistors, which prevents parasitic transistor leakage current and reduces parasitic capacitance
Implementation Method 4
A dual flexible bottom insulator (FBI) structure is implemented in nanostructure transistors, which prevents parasitic transistor leakage current
Data Source
AI summary
A device includes: a stack of nanostructure channels over a substrate; a gate structure wrapping around the stack; and a source/drain region on the substrate. The source/drain region includes: a first epitaxial layer in direct contact with the channels; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having higher germanium concentration than the first epitaxial layer. The device further includes a bottom isolation structure between the source/drain region and the substrate, the bottom isolation structure being a dielectric layer that is in direct contact with the source/drain region.