Biaxial Strained FET Devices Using Segmented Stressor Layers
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Solution Overview
Problem
The existing methods for manufacturing strained semiconductor devices using relaxed silicon germanium layers as a 'virtual substrate' result in high dislocation density, leading to undesirable consequences such as source/drain junction leakage and reduced channel mobility in MOSFETs due to the generation of misfit dislocations during strain relaxation.
Innovation Solution
A method is introduced where a buried stressor layer, such as silicon germanium, is used to induce strain in the semiconductor surface layer through edge relaxation, allowing for the formation of longitudinal strain in the active region of field effect transistors without exceeding the critical thickness for dislocation generation, thereby reducing dislocation density and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If a thick layer of silicon germanium is grown to exceed critical thickness for relaxation, then tensile strain is provided to the epitaxial silicon layer, but high dislocation density is generated causing source/drain junction leakage and reduced channel mobility
Solution Approach 1:
The silicon germanium layer is segmented into multiple thinner layers separated by silicon spacer layers. This segmentation allows each SiGe layer to remain below the critical thickness for dislocation generation while collectively providing the necessary tensile strain to the channel region through the cumulative effect of multiple strained layers.
Solution Approach 2:
Silicon spacer layers are introduced as intermediary elements between the SiGe layers. These spacer layers serve as stress transmission media that transfer the tensile strain from the SiGe layers to the overlying epitaxial silicon channel, enabling strain transfer without requiring a single thick relaxed SiGe layer that would generate dislocations.
2Stress or pressure
If a thick silicon germanium layer is used to provide strain, then strain relaxation occurs, but misfit dislocations are generated causing threading dislocations and extended defects
Solution Approach 1:
The SiGe layer is divided into multiple thin sub-layers, each thinner than the critical thickness for misfit dislocation formation. By segmenting the total strain-providing thickness into multiple thin layers separated by silicon spacers, the structure prevents the accumulation of misfit dislocations that would occur in a single thick layer while maintaining the overall strain effect.
Solution Approach 2:
Instead of using a single thick SiGe layer that exceeds critical thickness, the invention uses multiple partial layers that individually remain below the critical thickness threshold. The cumulative strain effect of multiple partial layers achieves the desired total strain without any single layer reaching the excessive thickness that triggers misfit dislocation formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively provides biaxial strain to the semiconductor surface layer, enhancing mobility and reducing defects, thus improving the performance and yield of integrated circuits by maintaining strain throughout processing steps while minimizing dislocation-related issues.
Implementation Method 1
The in-plane lattice parameter of the silicon germanium surface is similar to that of a bulk crystal of silicon germanium of the same composition. Silicon germanium alloys have larger lattice parameters than silicon. Hence the relaxed surface of the silicon germanium layer provides an in-plane lattice parameter larger than that of silicon. A subsequent thin layer of silicon is grown epitaxially on the relaxed surface of the silicon germanium layer. The thin epitaxial layer of silicon assumes the larger in-plane lattice parameter of the silicon germanium and grows in a strained state with bonds in the crystal lattice elongated in the growth plane.
Implementation Method 2
If the silicon germanium layer is thicker than the critical thickness, the strained lattice undergoes plastic deformation and the stress is relieved to some degree by the nucleation and propagation of misfit dislocations.
Implementation Method 3
Some fraction of misfit dislocations gives rise to threading dislocations (at least 104-105 cm−2) which propagate through the overlying strained silicon layer.
Implementation Method 4
A subsequent thin layer of silicon is grown epitaxially on the relaxed surface of the silicon germanium layer.
Data Source
AI summary
A process for forming contacts to a field effect transistor provides edge relaxation of a buried stressor layer, inducing strain in an initially relaxed surface semiconductor layer above the buried stressor layer. A process can start with a silicon or silicon-on-insulator substrate with a buried silicon germanium layer having an appropriate thickness and germanium concentration. Other stressor materials can be used. Trenches are etched through a pre-metal dielectric to the contacts of the FET. Etching extends further into the substrate, through the surface silicon layer, through the silicon germanium layer and into the substrate below the silicon germanium layer. The further etch is performed to a depth to allow for sufficient edge relaxation to induce a desired level of longitudinal strain to the surface layer of the FET. Subsequent processing forms contacts extending through the pre-metal dielectric and at least partially into the trenches within the substrate.