Strained FinFET Channel Regions via Epitaxial Growth
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Solution Overview
Problem
As device dimensions decrease, particularly gate pitch, the strain induced by lattice mismatched materials in FinFET devices becomes less effective and unstable, failing to adequately enhance the channel region's performance.
Innovation Solution
The method involves forming a fin structure with a vertical height in a substrate, creating a fin cavity by removing portions not covered by the gate structure, and depositing semiconductor materials within the cavity to induce strain on the channel region, using epitaxial growth processes to optimize stress and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are decreased to increase density, then productivity is improved, but the strain induced by lattice mismatched materials becomes less effective and stability deteriorates
Solution Approach 1:
The patent transitions from planar 2D strain induction to 3D vertical strain induction by forming semiconductor material layers above and below the channel region. This vertical dimension allows strain to be applied more effectively despite reduced device dimensions, maintaining reliability while improving density.
Solution Approach 2:
The patent applies different material compositions and strain characteristics to different locations: semiconductor material layers are formed selectively above and below the channel region with specific crystal orientations and compositions tailored to induce appropriate strain types (tensile or compressive) locally, optimizing performance for each region.
2Speed
If channel length is decreased to improve switching speed, then speed is improved, but short channel effects worsen
Solution Approach 1:
The patent changes the physical and chemical parameters of the semiconductor material layers, including crystal orientation, composition, and thickness, to induce strain that enhances carrier mobility and compensates for short channel effects, allowing faster switching while maintaining control.
Solution Approach 2:
The patent uses composite semiconductor structures combining different materials (e.g., SiGe, SiC, or other group IV materials) with different lattice constants to create strain through material composition rather than just geometric configuration, effectively counteracting short channel effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively enhances the strain on the channel region, improving charge carrier mobility and reducing leakage current, thereby increasing device performance and reliability.
Implementation Method 1
using epitaxial growth processes to optimize stress and reduce contact resistance
Implementation Method 2
the strain induced by lattice mismatched materials in FinFET devices
Data Source
AI summary
One illustrative method disclosed herein includes, among other things, removing at least a portion of a vertical height of portions of an overall fin structure that are not covered by a gate structure so as to result in the definition of a fin cavity in a layer of insulating material and the definition of a remaining portion of the overall fin structure that is positioned under the gate structure, wherein the remaining portion comprises a channel portion and a lower portion located under the channel portion. The method continues with the formation of a first semiconductor material within at least the fin cavity and the formation of a second semiconductor material on the first semiconductor material and on exposed edges of the channel portion.