Strained FinFET Source Drain Isolation via Low-k Spacer
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Solution Overview
Problem
The formation and integration of source drain regions in strained FinFETs are challenging due to epitaxy defects in the strain relaxation buffer (SRB) layer, leading to excessive source drain junction leakage and source drain punch through, as well as undoped portions of the strained fin bodies resulting in higher resistance.
Innovation Solution
A low-k spacer is formed between the fin stack and the SRB layer within the source and drain regions, isolating the strained fin body from the SRB layer and preventing excessive leakage and punch through, while allowing the strained fin body to be fully doped for lower resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If source drain regions contact the SRB layer having epitaxy defects, then manufacturing process is simplified, but excessive source drain junction leakage occurs
Solution Approach 1:
A low-k dielectric spacer is introduced as an intermediary layer between the source/drain regions and the SRB layer. This spacer physically separates the doped fin body from the defective SRB layer, preventing harmful interactions while allowing the source/drain regions to be formed without complex isolation structures. The spacer acts as a barrier that blocks defect propagation and reduces junction leakage.
2Ease of manufacture
If source drain regions contact the SRB layer, then manufacturing process is simplified, but source drain punch through occurs due to excessive dopant diffusion
Solution Approach 1:
The low-k dielectric spacer serves as a diffusion barrier between the source/drain regions and the SRB layer. During doping processes, the spacer prevents excessive dopant diffusion into the SRB layer, maintaining sharp junction profiles and preventing punch-through effects while simplifying the overall manufacturing process.
3Reliability
If portions of the strained fin bodies remain undoped, then source drain junction leakage is reduced, but resistance increases
Solution Approach 1:
The low-k dielectric spacer enables full doping of the strained fin body by providing a protective barrier that prevents harmful interactions with the SRB layer. This allows dopants to uniformly penetrate the entire fin body including regions adjacent to the SRB layer, achieving low resistance while the spacer prevents junction leakage by isolating the doped region from defects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The low-k spacer effectively limits source drain junction leakage and punch through, enabling full doping of the strained fin body and reducing resistance in strained FinFETs.
Implementation Method 1
forming a low-k spacer upon the gate structure sidewalls and within the fin void
Implementation Method 2
The strained fin bodies of strained FinFETs may be fabricated from a strained layer epitaxially grown upon on an SRB layer
Data Source
AI summary
A semiconductor structure, such as a strained FinFETs, includes a strain relief buffer (SRB) layer isolated and separated from a source and a drain by a second spacer simultaneously formed with a first spacer upon the sidewalls of a gate structure. The second spacer limits the source and drain from contacting the SRB layer thereby limiting source drain junction leakage. Further, the second spacer limits source and drain punch through to the SRB layer underneath a channel. An etch partially removes a SRB layer portion 24 within a fin stack. The etch undercuts the source and drain forming a fin void without under cutting the channel. The second spacer is formed by depositing spacer material with the fin void.