Strained Fin Stack Layout for Vertically Stacked CMOS Isolation
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Solution Overview
Problem
Existing technologies face challenges in fabricating finned semiconductor structures with different strain properties in electrically isolated portions of the same fins, which is crucial for enhancing carrier mobility in nFET and pFET devices.
Innovation Solution
A method is developed to fabricate stacked, fin-type CMOS devices by forming trenches in a dielectric layer, epitaxially growing semiconductor fin regions with different strain types within these trenches, and electrically isolating them using a dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different strain types are applied to different fin portions to enhance carrier mobility in nFET and pFET devices, then carrier mobility is improved, but the fabrication process complexity increases
Solution Approach 1:
The fin structure is segmented into multiple portions along its length, with each portion having different strain characteristics. This is achieved by creating recesses at different depths and filling them with different materials, allowing each segment to provide the appropriate strain for specific device types (nFET or pFET) while maintaining a unified fin structure.
Solution Approach 2:
Different regions of the fin structure are given different local properties through selective strain engineering. Specifically, certain fin portions are made tensile-strained while others are compressively strained, depending on the required device type. This local differentiation of strain properties enables optimized carrier mobility in different regions without requiring separate fin structures.
2Adaptability or versatility
If multiple semiconductor layers with different germanium percentages are used to create different strain types, then strain engineering capability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The strain characteristics of the fin structure are controlled by changing the germanium percentage parameter in different semiconductor layers. By precisely controlling the germanium content (e.g., 0-10%, 10-20%, 20-30% ranges), the patent achieves different strain types (tensile or compressive) in different fin portions, enabling versatile strain engineering while maintaining manageable manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of monolithic semiconductor structures with enhanced carrier mobility, increased transistor density, and the ability to achieve different strains in different portions of electrically isolated fin portions.
Implementation Method 1
epitaxially forming a bottom semiconductor base region within the at least one trench and adjoining the semiconductor substrate layer
Data Source
AI summary
A fin stack including compressively strained and tensile-strained semiconductor fin regions allows CMOS fabrication to form vertically stacked p-type FinFETs and n-type FinFETs. Aspect ratio trapping within a semiconductor base region within the fin stack provides a relaxed semiconductor base region on which uniaxially strained regions are grown. A dielectric layer may be formed to electrically isolate the compressively strained semiconductor fin region from the tensile-strained semiconductor fin region.