Strained FinFET Stress Layer for Carrier Mobility
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Solution Overview
Problem
Scaling down of MOSFETs leads to short channel effects, and it is challenging to apply suitable stress to the channel region of FinFETs to enhance carrier mobility and reduce on-state resistance.
Innovation Solution
A strained FinFET is manufactured by forming a stress layer on a semiconductor substrate, with a semiconductor fin having sidewalls extending in its length direction, and a gate dielectric and conductor are formed to apply stress to the fin, increasing carrier mobility and reducing on-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET size is scaled down to improve integration level and reduce manufacturing cost, then integration density increases, but short channel effects worsen
Solution Approach 1:
The patent transitions from planar MOSFET to FinFET architecture, adding vertical dimension to the channel structure. The fin structure provides three-dimensional gate control over the channel, enabling effective suppression of short channel effects at scaled dimensions while maintaining high integration density.
Solution Approach 2:
The channel region is segmented into multiple fins, with each fin providing an independent controlled path. This segmentation allows the gate to control the channel more effectively through multiple sidewalls, suppressing short channel effects while maintaining small footprint for high integration.
2Speed
If stress is applied to increase carrier mobility, then switching speed improves, but it becomes difficult to apply suitable stress to the channel region in FinFET
Solution Approach 1:
A separate stress layer is introduced as an intermediary component between the substrate and the fin structure. This stress layer applies mechanical stress to the fin channel region without interfering with the gate control or requiring modification of the existing FinFET fabrication process, enabling stress-induced mobility enhancement while maintaining manufacturing simplicity.
3Productivity
If gate length is reduced to improve integration, then device density increases, but gate control over depletion region charges decreases
Solution Approach 1:
The gate control is extended from two-dimensional planar contact to three-dimensional wraparound contact along the fin sidewalls. This vertical extension of gate control provides stronger electrostatic control over the channel and depletion region charges, maintaining threshold voltage stability even with reduced gate length and high device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stress layer effectively increases carrier mobility, reducing on-state resistance and enhancing switching speed of the device by applying stress to the semiconductor fin in the length direction.
Implementation Method 1
the stress layer extends below and in parallel with the semiconductor fin, and applies stress to the semiconductor fin in the length direction of the semiconductor fin
Data Source
AI summary
An FinFET and a method for manufacturing the same are disclosed. The FinFET comprises: a semiconductor substrate; a stress layer on the semiconductor substrate; a semiconductor fin on the stress layer, the semiconductor fin having two sidewalls extending in its length direction; a gate dielectric on the sidewalls of the semiconductor fin; a gate conductor on the gate dielectric; and a source region and a drain region at two ends of the semiconductor fin, wherein the stress layer extends below and in parallel with the semiconductor fin, and applies stress to the semiconductor fin in the length direction of the semiconductor fin.