Strained FinFET Elastic Strain Buffer Optimization
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Solution Overview
Problem
Conventional strained finFET devices face limitations in maximizing strain in the channel region due to plastic relaxation in thick SiGe strain layers, leading to defects and restricted strain thickness to avoid deformation, which limits hole or electron mobility enhancement.
Innovation Solution
The method involves forming a semiconductor fin with a strain-inducing layer and an active semiconductor layer on a substrate, where the strain-inducing layer is etched to relieve its strain and extend the fin depth below the strain-inducing layer, optimizing the elastic SiGe strain buffer to enhance strain in the channel region without plastic relaxation, using a thinner strain-inducing layer to apply maximum strain to the active semiconductor layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a thick strain-inducing layer is used to maximize strain in the channel region, then strain enhancement is improved, but plastic relaxation occurs causing defects and limiting further thickness increase
Solution Approach 1:
The device structure is segmented into distinct regions: a substrate, a strain-inducing layer of optimized thickness, and a channel region. The strain-inducing layer is positioned only where needed to provide strain to the channel, rather than extending through the entire device depth. This segmentation allows the strain layer to be thin enough to avoid plastic relaxation while still providing sufficient strain to the channel region for mobility enhancement.
Solution Approach 2:
The strain-inducing layer is applied locally only to specific regions where strain is needed in the channel, rather than uniformly throughout the entire device structure. This localized application allows the layer to be thin enough to maintain elastic strain without plastic relaxation, while still providing the necessary strain enhancement to the channel region for improved carrier mobility.
2Reliability
If the strain-inducing layer thickness is limited to avoid plastic relaxation, then defect formation is reduced, but the maximum strain that can be applied to the channel region is restricted
Solution Approach 1:
Instead of increasing strain layer thickness in the vertical dimension (which causes plastic relaxation), the invention optimizes the lateral dimensions and positioning of the strain-inducing layer. The layer is configured to extend laterally beneath the channel region and is positioned at an optimized depth, allowing it to provide maximum strain to the channel without requiring excessive thickness that would trigger plastic relaxation.
Solution Approach 2:
The invention changes the critical parameter from layer thickness to layer positioning and lateral extent. By optimizing the depth position and lateral dimensions of the strain-inducing layer rather than simply increasing its thickness, the device achieves maximum strain in the channel region while maintaining the layer thickness below the threshold for plastic relaxation.
3Reliability
If a thinner strain-inducing layer is used to avoid plastic relaxation, then reliability is improved, but the ability to induce sufficient strain in the channel region is reduced
Solution Approach 1:
The strain-inducing layer is positioned in advance at an optimized depth beneath the channel region, where it can most effectively induce strain without requiring excessive thickness. This preliminary positioning ensures that when the device is fabricated, the thin strain layer is already in the optimal location to provide maximum strain to the channel while maintaining elastic strain conditions without plastic relaxation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maximizes strain in the channel region, enhancing hole or electron mobility without defects, allowing for higher device speed and reduced junction leakage, while avoiding plastic relaxation and the need for thicker strain-inducing layers.
Implementation Method 1
the strain-inducing layer having a first lattice constant that is mismatched with respect to a second lattice constant of the semiconductor substrate
Implementation Method 2
etching the strain-inducing layer to increase a depth of the at least one fin and relieve a first strain applied to the strain-inducing layer while inducing a second strain applied to the at least one semiconductor fin
Implementation Method 3
optimizing the elastic SiGe strain buffer to enhance strain in the channel region without plastic relaxation
Data Source
AI summary
According to yet another non-limiting embodiment, a fin-type field effect transistor (finFET) including a strained channel region includes a semiconductor substrate extending along a first axis to define a length, a second axis perpendicular to the first axis to width, and a third direction perpendicular to the first and second axes to define a height. At least one semiconductor fin on an upper surface of the semiconductor substrate includes a semiconductor substrate portion on an upper surface of the semiconductor substrate, a strain-inducing portion on an upper surface of the semiconductor substrate portion, and an active semiconductor portion defining a strained channel region on an upper surface of the strain-inducing portion. A first height of the semiconductor substrate portion is greater than a second height of the strain-inducing portion.