Strained GAA Transistor Channels for Short-Channel Control
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Solution Overview
Problem
In the semiconductor industry, particularly in nanometer technology process nodes, the development of three-dimensional designs like Fin FETs and GAA FETs faces challenges due to the incomplete gate control over the channel region, leading to short-channel effects and reduced performance.
Innovation Solution
The implementation of a GAA FET manufacturing process that involves forming a fin structure with alternating semiconductor layers, wrapping a gate structure around semiconductor nanosheets, and using regrown source/drain layers with varying germanium-to-silicon atomic ratios to reduce strain mismatch and enhance carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a Fin FET structure is used to achieve three-dimensional design, then device density is improved, but gate control over the channel region is incomplete leading to short-channel effects
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional gate-all-around structure that completely surrounds the channel region. This dimensional change allows the gate to control the channel from all directions (top, bottom, and sides), achieving fuller depletion and eliminating short-channel effects while maintaining high device density through vertical stacking of multiple nanosheets.
Solution Approach 2:
The gate structure is nested around the channel region in a complete surrounding configuration, with the gate electrode wrapping around all surfaces of the semiconductor nanosheets. This nested arrangement ensures that the gate is in close proximity to all parts of the channel, providing uniform and complete gate control throughout the three-dimensional structure.
2Reliability
If regrown source/drain layers with varying germanium-to-silicon atomic ratios are used, then carrier mobility is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies different germanium-to-silicon atomic ratios to different regions of the source/drain layers. Specifically, the first regrown source/drain layer has a first germanium-to-silicon atomic ratio while the second regrown source/drain layer has a second germanium-to-silicon atomic ratio that is higher than the first. This local variation in material composition is strategically implemented to optimize strain distribution and carrier mobility in different parts of the device while managing manufacturing complexity through a systematic approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved carrier mobility and reduced short-channel effects by ensuring fuller depletion of the channel region and minimizing strain mismatch among the semiconductor nanosheets, thereby enhancing the performance of GAA FETs.
Implementation Method 1
regrown source/drain layers with varying germanium-to-silicon atomic ratios to reduce strain mismatch and enhance carrier mobility
Data Source
AI summary
The present disclosure provides a semiconductor device with a plurality of semiconductor channel layers. The semiconductor channel layers include a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer. A strain in the second semiconductor layer is different from a strain in the first semiconductor layer. A gate is disposed over the plurality of semiconductor channel layers.