Strained HOT MOSFET Fabrication for Carrier Mobility
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Solution Overview
Problem
Conventional CMOS device fabrication methods for N channel and P channel transistors are complex and require different crystallographic orientations for tensile and compressive strain, necessitating a simpler approach to optimize transistor performance.
Innovation Solution
A semiconductor fabrication method involving a semiconductor structure with alternating crystallographic orientations and materials, including a buried insulating layer, where sacrificial regions are etched to form strained semiconductor layers for N and P channel transistors, optimizing their performance by using SiGe or SiC for enhanced carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different crystallographic orientations are used for N channel and P channel transistors to achieve tensile and compressive strain, then transistor performance is optimized, but fabrication complexity increases
Solution Approach 1:
The semiconductor structure is segmented into multiple layers with different crystallographic orientations. The first semiconductor layer has a first crystallographic orientation while the second semiconductor layer has a second crystallographic orientation, allowing independent optimization of N channel and P channel transistors without requiring the entire substrate to be reoriented for each device type.
Solution Approach 2:
The patent employs a composite semiconductor structure where layers of different materials and crystallographic orientations are stacked together. The first semiconductor layer and second semiconductor layer are formed on opposite sides of the buried insulating layer, creating a composite structure that provides both tensile strain (for N channel) and compressive strain (for P channel) environments simultaneously.
2Reliability
If multiple semiconductor layers with different crystallographic orientations are stacked, then strain optimization is achieved, but manufacturing process complexity increases
Solution Approach 1:
The solution moves from a planar single-layer structure to a vertical multi-layer stacking architecture. By utilizing the vertical dimension, the patent accommodates different crystallographic orientations in the first and second semiconductor layers without requiring complex lateral processing variations, thereby simplifying the manufacturing approach compared to traditional methods.
Solution Approach 2:
The buried insulating layer is formed between the first and second semiconductor layers in advance, establishing the structural framework before the semiconductor layers are deposited. This preliminary action enables subsequent layers to be formed with their respective crystallographic orientations without requiring post-formation reorientation or complex alignment procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method simplifies CMOS device fabrication while optimizing N and P channel transistor performance by leveraging strained semiconductor layers, improving carrier mobility and device efficiency.
Implementation Method 1
the N channel transistor is formed on a first crystallographic orientation semiconductor which is tensile strained, and the P channel transistor is formed on a second crystallographic orientation semiconductor which is compressively strained
Data Source
AI summary
A strained HOT MOSFET fabrication method. The MOSFET fabrication method includes providing a semiconductor structure which includes (a) a first semiconductor layer having a first crystallographic orientation, (b) a buried insulating layer on top of the first semiconductor layer, (c) a second semiconductor layer on top of the buried oxide layer. The second semiconductor layer has a second crystallographic orientation different from the first crystallographic orientation. The method further includes forming a third semiconductor layer on top of the first semiconductor layer which has the first crystallographic orientation. The method further includes forming a fourth semiconductor layer on top of the third semiconductor layer. The fourth semiconductor layer (a) comprises a different material than that of the third semiconductor layer, and (b) has the first crystallographic orientation.