Strained Isolation Regions for MOSFET Carrier Mobility
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Solution Overview
Problem
Existing methods for inducing strain in MOSFET transistors, such as using semiconductor alloy layers or high-stress films, face challenges like junction leakage, cost, and limited stress application, necessitating an efficient and cost-effective method to enhance transistor performance.
Innovation Solution
The method involves forming strained isolation regions by creating isolation trenches in a semiconductor substrate, filling them with a dielectric material, recessing the material, and applying a high-stress film over the transistor structure to introduce tensile or compressive strain, thereby enhancing carrier mobility without direct contact with the stressor and the substrate, which reduces junction leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a blanket semiconductor alloy layer is used to induce strain, then carrier mobility is enhanced, but junction leakage increases and processing complexity increases
Solution Approach 1:
The blanket semiconductor alloy layer is segmented into localized strained isolation regions formed only in specific isolation trenches between transistor devices. This segmentation eliminates the continuous alloy layer that causes junction leakage while preserving strain-induced carrier mobility enhancement in the channel regions where it is needed.
Solution Approach 2:
Strain is applied locally only in the isolation regions between devices rather than uniformly across the entire substrate. The strained isolation regions are formed with specific materials (e.g., SiGe) that induce tensile strain in adjacent n-channel devices and compressive strain in adjacent p-channel devices, providing localized quality enhancement without blanket coverage.
2Reliability
If a high-stress film is formed over the completed transistor structure, then carrier mobility is enhanced, but the amount of stress is limited by gap-fill capabilities and etching window
Solution Approach 1:
Instead of applying stress only from the top surface (vertical dimension), the strain is introduced through lateral dimensions by forming strained isolation regions on the sidewalls and surfaces of isolation trenches. This multi-dimensional approach allows stress to be applied from multiple directions (top and sidewalls) simultaneously, overcoming the limitations of single-direction high-stress film application.
Solution Approach 2:
The strained isolation regions are formed during the isolation trench filling process, before the transistor gate and source/drain structures are completed. This preliminary action allows the strain to be established early in the fabrication sequence, providing a foundation for subsequent device formation without being constrained by later gap-fill or etching window limitations.
3Reliability
If semiconductor alloy layers are epitaxially grown, then strain is introduced, but the process is costly and difficult to control germanium level
Solution Approach 1:
Silicon oxide or silicon oxynitride dielectric materials serve as intermediaries in the isolation trench filling process. These materials can be deposited using standard CVD or PECVD techniques and then selectively removed or modified to create strained isolation regions. This intermediary approach avoids direct epitaxial growth of complex alloy layers while still enabling strain introduction through subsequent material deposition or modification steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases carrier mobility in MOSFET transistors by applying controlled strain, improving performance while avoiding junction leakage issues and cost constraints associated with traditional methods.
Implementation Method 1
a high-stress film is formed over a completed transistor structure formed in a silicon substrate. The high-stress film or stressor exerts significant influence on the channel, modifying the silicon lattice spacing in the channel region, and thus introducing strain in the channel region.
Implementation Method 2
The difference in the lattice structure imparts strain in the overlying semiconductor layer to increase carrier mobility.
Data Source
AI summary
A method of forming an isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.