Strained Nano-FET Channel Structure for Mobility and Resistance

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Solution Overview

Problem

As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in maintaining carrier mobility and reducing resistance in channel regions, which affect device performance.

Innovation Solution

The implementation of sacrificial layers that induce bi-directional strain in the channel regions of nano-FETs, which are subsequently removed without altering the strain, thereby enhancing carrier mobility and reducing resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but carrier mobility deteriorates and resistance increases in channel regions

Engineering Contradiction:
Improveintegration densityVSAvoidcarrier mobility
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by forming sacrificial layers with different lattice constants than the channel region material before the channel region is fully formed. These sacrificial layers induce bi-directional strain in the channel region during subsequent growth or deposition processes. The strain is introduced in advance to compensate for the degradation of carrier mobility that would otherwise occur due to reduced minimum feature sizes, thereby maintaining reliable device performance while achieving high integration density.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but resistance increases in channel regions

Engineering Contradiction:
Improveintegration densityVSAvoidresistance
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by forming sacrificial layers with different lattice constants than the channel region material before the channel region is fully formed. These sacrificial layers induce bi-directional strain in the channel region during subsequent growth or deposition processes. The strain is introduced in advance to compensate for the degradation of carrier mobility that would otherwise occur due to reduced minimum feature sizes, thereby maintaining reliable device performance while achieving high integration density.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies parameter changes by utilizing sacrificial layers with specifically selected lattice constants that differ from the channel region material. By controlling the lattice constant parameter of the sacrificial layer, the patent induces controlled bi-directional strain in the channel region, which modifies the electrical properties (carrier mobility and resistance) of the channel region without changing its physical dimensions, thereby reducing resistance while maintaining high integration density.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If sacrificial layers are used to induce strain in channel regions, then carrier mobility improves and resistance reduces, but device complexity increases

Engineering Contradiction:
Improvecarrier mobilityVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies the taking out principle by introducing sacrificial layers that are subsequently removed after inducing the desired bi-directional strain in the channel region. The sacrificial layers serve only as temporary strain-inducing elements and are extracted from the final device structure. This approach allows the channel region to achieve improved carrier mobility and reduced resistance through strain, while the final device complexity is minimized by removing the sacrificial components after they have served their purpose.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies the intermediary principle by using sacrificial layers as temporary mediator structures that facilitate the introduction of bi-directional strain into the channel region. These sacrificial layers act as intermediaries between the manufacturing process and the final device structure, enabling strain induction without becoming permanent parts of the device. The sacrificial layers are removed after inducing the necessary strain, thus improving carrier mobility while avoiding permanent increases in device complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The bi-directional strain in the channel regions improves carrier mobility and reduces resistance, leading to enhanced performance of semiconductor devices.

Implementation Method 1

sacrificial layers that induce bi-directional strain in the channel regions

Methodology Applied
Scientific EffectStrain: Deformation

Implementation Method 2

the bi-directional strain induced in the channel regions may change average lattice constants of the channel regions

Methodology Applied
Scientific EffectLattice constant:

Data Source

PatentUS20260068253A1Semiconductor device and method
Publication Date: 2026.03.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20260068253A1 patent drawing
  • US20260068253A1 patent drawing
  • US20260068253A1 patent drawing

AI summary

A semiconductor device and the method of forming the same are provided. The semiconductor device may include an n-type region and a p-type region. The n-type region may include a first portion of a semiconductor substrate and a first nanostructure with a same semiconductor material as the semiconductor substrate. The first nanostructure may include a first average lattice constant in a first direction and a second average lattice constant in a second direction. The p-type region may include a second portion of the semiconductor substrate and a second nanostructure with the same semiconductor material as the semiconductor substrate. The second nanostructure may include a third average lattice constant in a third direction parallel with the first direction and a fourth average lattice constant in a fourth direction parallel with the second direction. The third average lattice constant maybe smaller than the first average lattice constant.