Strained Stacked Nanosheet FETs via Selective Etch

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Solution Overview

Problem

Current nanosheet field effect transistors (FETs) face challenges in achieving strained nanosheets and quantum well structures, which are essential for enhancing mobility and transport in CMOS scaling due to difficulties in electrostatic control and material limitations.

Innovation Solution

A process involving the growth of an epitaxial crystalline stack with sub-stacks containing sacrificial and non-sacrificial layers, where the non-sacrificial layers are kept below critical thickness, and sacrificial layers are selectively removed to form pillar structures, allowing for strained and quantum well properties in nanosheets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If single material nanosheets are used for electrostatic control, then electrostatic control is improved, but mobility enhancement through strain is difficult to achieve

Engineering Contradiction:

Improveelectrostatic controlVSAvoidstrain implementation

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent uses composite material stacks consisting of multiple layers including Si, SiGe, and Ge layers arranged in specific configurations. These composite structures enable both electrostatic control through the thin overall stack and strain enhancement through the lattice-mismatched SiGe/Si interfaces, resolving the contradiction between electrostatic control and strain implementation

Inventive Principle:

Principle #40Composite materials

2Reliability

If nanosheet thickness is reduced for electrostatic control, then electrostatic control is improved, but strain implementation becomes more difficult

Engineering Contradiction:

Improveelectrostatic controlVSAvoidstrain implementation

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating specific strained regions within the nanosheet stack. SiGe layers are strategically positioned to induce local strain in adjacent Si channels, while maintaining overall thin thickness for electrostatic control. This localized strain approach enables mobility enhancement without compromising electrostatic control

Inventive Principle:

Principle #3Local quality

3Reliability

If epitaxial crystalline stacks with multiple layers are created, then strained and quantum well structures are achieved, but maintaining common lattice parameter and low defectivity becomes challenging

Engineering Contradiction:

Improvetransport propertiesVSAvoidlattice parameter uniformity

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent carefully controls layer thicknesses to remain below critical thickness values, preventing misfit dislocation formation. By adjusting composition and thickness parameters of SiGe and Ge layers, the patent achieves strain and quantum well effects while maintaining a common lattice parameter throughout the stack, ensuring low defectivity

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the fabrication of nanosheets with low defectivity and strained or quantum well structures, improving mobility and transport properties, thereby supporting CMOS scaling with reduced defects and maintaining a common lattice parameter throughout the process.

Implementation Method 1

growing an epitaxial crystalline initial stack of one or more sub-stacks

Methodology Applied

Scientific EffectEpitaxy: Epitaxy

Implementation Method 2

selectively removing sacrificial layers A to all non-sacrificial layers B and C

Methodology Applied

Scientific EffectSelective etching:

Data Source

PatentUS10170549B2Strained stacked nanosheet FETs and/or quantum well stacked nanosheet

Publication Date: 2019.01.01 SAMSUNG ELECTRONICS CO LTD

AI summary

Exemplary embodiments provide for fabricating a nanosheet stack structure having one or more sub-stacks. Aspects of the exemplary embodiments include: growing an epitaxial crystalline initial stack of one or more sub-stacks, each of the sub-stacks having at least three layers, a sacrificial layer A, and at least two different non-sacrificial layers B and C having different material properties, wherein the non-sacrificial layers B and C layers are kept below a thermodynamic or kinetic critical thickness corresponding to metastability during all processing, and wherein the sacrificial layer An is placed only at a top or a bottom of each of the sub-stacks, and each of the sub-stacks is connected to an adjacent sub-stack at the top or the bottom using one of the sacrificial layers A; proceeding with fabrication flow of nanosheet devices, such that pillar structures are formed at each end of the epitaxial crystalline stack that to hold the nanosheets in place after selective etch of the sacrificial layers; and selectively removing sacrificial layers A to all non-sacrificial layers B and C, while the remaining layers in the stack are held in place by the pillar structures so that after removal of the sacrificial layers An, each of the sub-stacks contains the non-sacrificial layers B and C.