Strained Nanosheet GAAFETs on SOI Without SiGe Buffer Limits
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Solution Overview
Problem
The use of a SiGe strain-relaxed buffer (SRB) layer in semiconductor manufacturing degrades channel quality and limits performance due to restricted channel strain and crystal quality issues, and is also costly.
Innovation Solution
Replace the SRB layer with a partially-strained or fully strain-relaxed Si/SiGe bi-layer as a foundation for forming strained channels, using a modified silicon-on-insulator (SOI) structure to grow nanosheet transistors with compressively strained SiGe channels for PMOS devices and tensile-strained silicon channels for NMOS devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a SiGe strain-relaxed buffer (SRB) layer is used in semiconductor manufacturing, then crystal quality is improved, but channel strain is restricted and performance is limited
Solution Approach 1:
The patent segments the buffer structure into multiple functional layers: a SiGe strain-relaxed buffer layer for crystal quality, followed by a separate SiGe source/drain layer for channel strain, and finally the silicon channel layer. This segmentation allows each layer to independently fulfill its specific function without compromising the others.
Solution Approach 2:
The patent applies local quality by having different regions of the structure serve different purposes: the SRB layer provides crystal quality in the bulk region, while the SiGe source/drain region provides localized strain in the channel region. This spatial differentiation of material properties resolves the contradiction between maintaining crystal quality and enabling channel strain.
2Manufacturing precision
If a SiGe strain-relaxed buffer (SRB) layer is used, then crystal quality is improved, but manufacturing cost increases
Solution Approach 1:
The SiGe source/drain layer serves multiple functions: it acts as a strain-inducing layer for the channel, provides electrical contact regions, and can be selectively removed in certain device configurations. This multi-functionality reduces the need for separate dedicated layers, thereby reducing manufacturing complexity and cost while maintaining crystal quality through the SRB layer.
3Productivity
If channel dimensions are scaled down, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by pre-forming the SiGe strain-relaxed buffer layer and SiGe source/drain layers with optimized compositions and thicknesses before final channel formation. This preliminary preparation of strain and crystal quality ensures that subsequent channel scaling can be performed with reduced manufacturing complexity, as the critical strain and quality parameters are already established.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases carrier mobility, enhancing transistor performance and allowing for a wider range of germanium concentrations in SiGe films, improving device performance and reducing manufacturing costs.
Implementation Method 1
forming a first nanosheet layer comprising compressive strained silicon germanium (SiGe)
Implementation Method 2
Replace the SRB layer with a partially-strained or fully strain-relaxed Si/SiGe bi-layer
Data Source
AI summary
A strain-relaxed silicon/silicon germanium (Si/SiGe) bi-layer can be used as a foundation for constructing strained channel transistors in the form of nanosheet gate all-around field effect transistors (GAAFETs). The bi-layer can be formed using a modified silicon-on-insulator process. A superlattice can then be epitaxially grown on the bi-layer to provide either compressively strained SiGe channels for a p-type metal oxide semiconductor (PMOS) device, or tensile-strained silicon channels for an n-type metal oxide semiconductor (NMOS) device. Composition and strain of the bi-layer can influence performance of the strained channel devices.