Strained Nanosheet Channels Using an Interposer Stress Layer

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Solution Overview

Problem

The semiconductor industry faces challenges in scaling down semiconductor IC dimensions while maintaining gate control and mitigating short-channel effects, particularly in multi-gate devices like FinFETs and GAA transistors, which require advanced manufacturing processes to enhance performance and reduce complexity.

Innovation Solution

The introduction of a method to form strained nanosheet channels by applying stress to nanosheet channels using an interposer layer, which involves forming and expanding a germanium-free interposer layer to apply compressive stress, thereby enhancing gate control and reducing diffusion issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multi-gate devices like FinFETs and GAA transistors are used to improve gate control and reduce short-channel effects, then gate control and device performance are improved, but manufacturing process complexity increases

Engineering Contradiction:
Improvegate controlVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A sacrificial layer is introduced as an intermediary component during the manufacturing process. This sacrificial layer is deposited over the channel region, patterned to define source and drain regions, and subsequently removed to create voids that are filled with conductive material. This intermediary approach enables precise formation of source/drain regions and stress application to the channel without requiring complex direct patterning methods, thereby improving gate control while managing manufacturing complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The source and drain regions are formed in advance before the final gate structure is completed. The sacrificial layer is deposited and patterned prior to gate formation, allowing preliminary definition of active regions. This preliminary action enables better control of the channel region and facilitates subsequent gate-all-around formation without increasing overall process complexity

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the minimum feature size is scaled down to improve production efficiency and lower costs, then productivity and cost-effectiveness are improved, but manufacturing process complexity increases

Engineering Contradiction:
Improveproduction efficiencyVSAvoidmanufacturing process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Traditional mechanical direct-patterning methods for forming source and drain regions are replaced with a chemical deposition and removal process. The sacrificial layer is deposited using chemical vapor deposition or atomic layer deposition, then selectively removed through chemical etching or oxidation. This substitution of mechanical patterning with chemical processes enables better control at scaled dimensions while maintaining manufacturing efficiency

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The manufacturing approach changes from direct physical patterning to a multi-step process involving deposition parameters, temperature control, and chemical reaction parameters. By controlling deposition thickness, etch selectivity, and removal conditions, precise feature formation is achieved at scaled dimensions. This parameter-based control enables continued scaling while managing process complexity through well-established semiconductor fabrication techniques

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves gate control and reduces diffusion in multi-gate devices, leading to better performance and reduced complexity in semiconductor manufacturing processes.

Implementation Method 1

forming and expanding a germanium-free interposer layer to apply compressive stress

Methodology Applied
Scientific EffectCompressive stress: Compression

Implementation Method 2

reducing diffusion issues

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Data Source

PatentUS20250351485A1Strained channel regions
Publication Date: 2025.11.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250351485A1 patent drawing
  • US20250351485A1 patent drawing
  • US20250351485A1 patent drawing

AI summary

Provided are semiconductor devices with strained nanosheet channels and methods for fabricating such devices. A method includes forming a fin comprising a first material lying over a second material; forming a sacrificial gate over the fin, wherein a channel region of the fin including the first material and the second material lies directly under the sacrificial gate and between two non-channel regions of the fin including the first material and the second material; removing the non-channel regions of the fin; performing a process to replace the second material in the channel region of the fin with a third material; forming source/drain features in the non-channel regions; removing the sacrificial gate; removing the third material; and forming a gate over the fin.