Strained Nanowire CMOS Structure With Alternating Epitaxial Layers
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Solution Overview
Problem
The scaling down of Integrated Circuits (ICs) has increased complexity in processing and manufacturing, requiring advancements in IC processing and manufacturing techniques, particularly in the development of Fin Field-Effect Transistors (FinFETs) with Gate-All-Around (GAA) structures to improve electrical performance.
Innovation Solution
The formation of FinFETs with GAA structures involves the use of alternating epitaxial layer structures, where silicon germanium layers are grown to form nanowire structures for n-type FinFETs and stressed layers for p-type FinFETs, utilizing low-pressure chemical vapor deposition (LPCVD) and other processes to exert stress in the channel regions, enhancing electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FinFETs with GAA structures are developed to improve electrical performance, then device efficiency is enhanced, but processing and manufacturing complexity increases
Solution Approach 1:
The channel region is segmented into multiple alternating epitaxial layers of different semiconductor materials (e.g., Si/SiGe), creating a stacked nanowire structure. This segmentation enables independent stress control in each layer, improving electrical performance while maintaining manageable processing through modular fabrication steps
Solution Approach 2:
The patent employs composite material structures with alternating layers of different semiconductor materials (silicon, silicon germanium, silicon carbide) in the channel region. These composite structures provide both mechanical stress control and electrical performance enhancement, resolving the contradiction between improved reliability and increased complexity by using material composition rather than structural complexity
2Reliability
If alternating epitaxial layer structures are used to exert stress in channel regions, then electrical performance is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent controls stress in the channel region by varying material composition parameters (germanium content, carbon content) and layer thickness parameters in the alternating epitaxial structure. By adjusting these parameters during epitaxial growth, the desired stress state (tensile or compressive) is achieved without requiring extreme manufacturing precision
Solution Approach 2:
The alternating epitaxial layer structure exerts stress on the channel region through inherent material property differences (lattice mismatch between Si and SiGe layers). This self-stressing mechanism eliminates the need for external stress application equipment or complex post-processing steps, reducing manufacturing precision requirements while maintaining electrical performance enhancement
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the electrical performance of FinFETs by exerting compressive stress in p-type FinFETs and tensile stress in n-type FinFETs, leading to enhanced device efficiency and reduced manufacturing costs through the use of similar materials and processing techniques for both types.
Implementation Method 1
utilizing low-pressure chemical vapor deposition (LPCVD) and other processes to exert stress in the channel regions
Implementation Method 2
forming a first fin and a second fin, each of the first fin and the second fin comprising an alternating epitaxial structure, the alternating epitaxial structure having a plurality of epitaxial layers
Data Source
AI summary
Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.