Strained Semiconductor Nanowire via Embedded Stress Generators

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Solution Overview

Problem

Introducing strain into semiconductor nanowires is challenging due to their small lateral dimensions, which affects charge carrier mobility in field effect transistors.

Innovation Solution

A semiconductor structure is formed with semiconductor nanowires suspended over insulator layers and embedded stress-generating materials in trenches within pad portions, applying tensile or compressive strain along the nanowires' lengthwise direction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If strain is introduced into semiconductor nanowires to improve charge carrier mobility, then transistor performance is improved, but the small lateral dimensions of nanowires make strain introduction difficult

Engineering Contradiction:
Improvecharge carrier mobilityVSAvoidstrain introduction difficulty
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent transitions from attempting to introduce strain directly into the nanowire (1D structure) to embedding stress-generating materials in the surrounding pad portions (3D structures), thereby applying strain to the nanowire indirectly through its supporting structures. This dimensional approach resolves the difficulty of directly straining the nanowire while achieving the desired stress effect.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces stress-generating materials as intermediary elements embedded in trenches within the pad portions. These materials serve as mediators that generate stress which is then transferred to the nanowire, enabling strain introduction without directly manipulating the nanowire itself, thus overcoming the manufacturing difficulty associated with direct nanowire strain introduction.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If stress-generating materials are embedded in pad portions, then strain is applied to nanowires, but additional manufacturing steps are required

Engineering Contradiction:
Improvestrain applicationVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent performs preliminary actions by forming trenches in the pad portions and embedding stress-generating materials before final nanowire fabrication or device assembly. This advance preparation ensures that the strain is already in place when the nanowire is formed or attached, simplifying the overall process by eliminating the need for subsequent strain introduction steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent embeds stress-generating materials within trenches that are themselves embedded in the pad portions, creating a nested structure. The stress-generating materials are nested within the pad portions, which in turn support the nanowire. This nested arrangement efficiently integrates multiple functions (structural support and strain application) into a compact configuration, managing device complexity through hierarchical integration.

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The strain enhances minority charge carrier mobility in field effect transistors, improving transistor performance by manipulating stress within the nanowires.

Implementation Method 1

The semiconductor nanowire is strained along a lengthwise direction by a stress generated by the at least one stress-generating material portion

Methodology Applied
Scientific EffectStress generation through lattice mismatch: Deformation

Data Source

PatentUS10580894B2Strained semiconductor nanowire
Publication Date: 2020.03.03 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10580894B2 patent drawing
  • US10580894B2 patent drawing
  • US10580894B2 patent drawing

AI summary

At least one semiconductor nanowire laterally abutted by a pair of semiconductor pad portions is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor nanowire such that the at least one semiconductor nanowire is suspended. A temporary fill material is deposited over the at least one semiconductor nanowire, and is planarized to physically expose top surfaces of the pair of semiconductor pad portions. Trenches are formed within the pair of semiconductor pad portions, and are filled with stress-generating materials. The temporary fill material is subsequently removed. The at least one semiconductor nanowire is strained along the lengthwise direction with a tensile strain or a compressive strain.