Uniaxially Strained Nanowire Transistors for Mobility Scaling
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Solution Overview
Problem
The challenge in semiconductor device fabrication lies in maintaining mobility improvement and short channel control as microelectronic device dimensions scale past the 15 nanometer node, particularly in enhancing electron and/or hole mobility in nanowire-based transistors.
Innovation Solution
The implementation of uniaxially strained nanowire structures, where nanowires are fabricated with either uniaxial tensile or compressive strain, integrated with a gate electrode stack surrounding discrete channel regions, to improve channel mobility for both NMOS and PMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are scaled down past 15nm node, then device density is improved, but mobility improvement and short channel control deteriorate
Solution Approach 1:
The patent applies uniaxial strain locally to the nanowire channel region through selectively oriented sacrificial layers, creating localized stress fields that enhance carrier mobility specifically in the channel without affecting other device regions. This local quality modification allows mobility improvement at scaled dimensions where conventional approaches fail.
Solution Approach 2:
The patent changes the physical state of the nanowire channel by introducing uniaxial strain through epitaxially grown sacrificial layers with different lattice constants. This parameter change (applying mechanical strain) fundamentally alters the band structure and carrier transport properties, enabling mobility enhancement at 15nm and below where traditional scaling alone cannot maintain performance.
2Ease of manufacture
If conventional nanowire structures are used, then fabrication is simpler, but electron and hole mobility improvement is insufficient
Solution Approach 1:
The patent introduces sacrificial nanowire layers as intermediary structures during fabrication. These sacrificial layers are grown with specific crystal orientations and lattice constants that induce uniaxial strain in the channel. After serving their strain-inducing purpose, they are selectively removed, having transferred their mechanical stress to the channel structure. This intermediary approach enables complex strain engineering without permanently complicating the device structure.
Solution Approach 2:
The patent employs composite material structures combining different semiconductor layers (e.g., Si/SiGe/Si stacks) with distinct lattice constants and mechanical properties. The sacrificial layers are composed of materials with specific elastic and lattice properties that enable controlled strain transfer to the channel region. This composite approach allows independent optimization of strain characteristics and fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electron and hole mobility by applying appropriate strain in the channel regions of nanowire-based transistors, effectively addressing the limitations of existing technologies in scaling and performance.
Implementation Method 1
Each of the uniaxially strained nanowires includes a discrete channel region disposed in the uniaxially strained nanowire. The discrete channel region has a current flow direction along the direction of the uniaxial strain.
Data Source
AI summary
Uniaxially strained nanowire structures are described. For example, a semiconductor device includes a plurality of vertically stacked uniaxially strained nanowires disposed above a substrate. Each of the uniaxially strained nanowires includes a discrete channel region disposed in the uniaxially strained nanowire. The discrete channel region has a current flow direction along the direction of the uniaxial strain. Source and drain regions are disposed in the nanowire, on either side of the discrete channel region. A gate electrode stack completely surrounds the discrete channel regions.