Strained NMOS and PMOS Layout for Opposing Channel Stress
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Solution Overview
Problem
Existing methods struggle to simultaneously produce N-channel and P-channel MOS transistors with different stress constraints, particularly in small dimensions, which hinders performance improvement in semiconductor-on-insulator structures.
Innovation Solution
A method for manufacturing N-channel and P-channel MOS transistors with different constraints by forming insulated grids on transverse trenches, connecting transistors to high and low supply potentials, and applying stress layers using silicon nitride and silicon-germanium to achieve desired stress conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If known processes are used to simultaneously produce P-channel and N-channel transistors, then both transistor types can be manufactured, but it is difficult to reconcile different stress constraints for each type, particularly in small dimensions
Solution Approach 1:
The substrate is divided into two separate bands: a first band for N-channel transistors and a second band for P-channel transistors. Each band receives tailored stress layers appropriate for its transistor type, allowing different stress constraints to be applied simultaneously without process reconciliation issues.
Solution Approach 2:
Different stress layer configurations are applied to different regions of the substrate. The first band receives a stress layer configuration optimized for N-channel transistors (tensile stress), while the second band receives a configuration optimized for P-channel transistors (compressive stress), enabling locally optimized performance.
2Speed
If stress layers are applied to improve transistor performance, then transistor speed and performance are enhanced, but the manufacturing process becomes more complex
Solution Approach 1:
The manufacturing process segments the substrate into distinct bands early in the process, allowing stress layers to be applied independently to each band. This segmentation simplifies the overall manufacturing complexity by treating each band as a separate manufacturing zone with its own optimized process parameters.
Solution Approach 2:
The stress layers are applied to the semiconductor layer before certain subsequent processing steps. This preliminary application of stress layers ensures that the performance-enhancing stress is established early in the manufacturing process, allowing subsequent steps to proceed without disrupting the stress configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables the production of fast N-channel and P-channel transistors with opposing stress constraints, resulting in enhanced performance and speed of integrated circuits.
Implementation Method 1
perform a heat treatment to relax the stress layer, adapted to retain at least some of the stresses of the tape and slabs
Implementation Method 2
the stress layer is made of silicon nitride formed in step a) by plasma-assisted chemical vapor deposition
Implementation Method 3
perform a heat treatment to relax the stress layer, adapted to retain at least some of the stresses of the tape and slabs
Implementation Method 4
the stress layer is made of silicon-germanium and is epitaxially grown in step a) on the substrate
Data Source
Figure 1A~1D
Figure 2A~2D
Figure 3A~3D
AI summary
The invention relates to an electronic chip comprising an insulating layer on a substrate; longitudinal trenches (250L) between and on either side of first (54N) and second (54P) strips side by side; transverse trenches (250W) from one edge to the other of the first strip, extending through the insulating layer and into the substrate, the insulating layer of the first strip being covered, between the transverse and longitudinal trenches, with semiconductor slabs (260) strained in tension, and the insulating layer of the second strip being covered, facing the slabs and between the longitudinal trenches, with semiconductor portions of a ribbon (252) strained in longitudinal compression and/or in transverse tension ; and N-channel MOS transistors being located, in the first strip, in and on the plates and P-channel MOS transistors being located, in the second strip, in and on said ribbon portions.