Strained Channel PMOS Devices Using Sub-Room Temperature Implantation
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Solution Overview
Problem
Conventional strain implant/anneal processes for MOS devices suffer from high manufacturing costs, integration issues, and low device reliability due to high residual end-of-range disorder, which reduces yield and performance.
Innovation Solution
Sub-room temperature implantation of strain-inducing species like Ge, Sn, and Pb, followed by high-temperature annealing for solid phase epitaxy, which reduces end-of-range disorder and increases strain in the substrate lattice beyond equilibrium solubility limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional strain implant/anneal processes are used, then mechanical strain is introduced into the channel region, but high residual end-of-range disorder results in reduced device reliability and yield
Solution Approach 1:
The patent applies parameter changes by modifying the implantation temperature to sub-room temperature (below 273K) and adjusting the annealing temperature and time parameters. This resolves the contradiction by changing the physical state parameters during implantation to reduce atomic recoil and end-of-range disorder, while maintaining the strain introduction function. The specific parameter changes include: implantation temperature ≤273K, annealing temperature 900-1100°C, and annealing time 5-30 seconds.
Solution Approach 2:
The patent applies preliminary action by performing sub-room temperature implantation before annealing to create an amorphous region with minimal end-of-range disorder. This preliminary low-temperature implantation step prepares the substrate in a controlled state, preventing the formation of dislocation loops before the annealing process begins. The amorphous region formed at low temperature serves as a clean slate for subsequent strain introduction during annealing.
2Ease of manufacture
If room temperature implantation is used, then the process is simpler, but appreciable recoil of substrate atoms occurs reducing amorphous zone expansion and increasing end-of-range disorder
Solution Approach 1:
The patent changes the temperature parameter from room temperature to sub-room temperature (≤273K) during implantation. This parameter change reduces the thermal energy of substrate atoms, minimizing atomic recoil and expanding the amorphous zone while reducing end-of-range disorder. Although this adds temperature control complexity, it significantly improves the quality of the amorphous region and reduces defects.
Solution Approach 2:
The patent applies beforehand cushioning by using low temperature implantation to cushion against atomic recoil effects. The reduced thermal energy at sub-room temperature acts as a cushion that prevents substrate atoms from recoiling excessively during ion implantation, thereby expanding the amorphous zone and reducing end-of-range disorder before annealing occurs.
3Reliability
If long annealing time is used, then strain inducing species are incorporated into the lattice, but manufacturing cost increases and process integration becomes difficult
Solution Approach 1:
The patent changes the annealing parameters by using high temperature (900-1100°C) combined with short time (5-30 seconds). This parameter combination achieves effective strain introduction through solid phase epitaxy without the need for prolonged annealing. The high temperature provides sufficient thermal energy for rapid atomic diffusion and lattice incorporation, while the short duration prevents excessive grain growth and maintains process integration compatibility.
Solution Approach 2:
The patent applies periodic action by using rapid thermal annealing with a sharp temperature spike followed by quick cooling. This periodic thermal profile delivers the necessary thermal energy in a concentrated pulse, enabling strain inducing species to incorporate into the lattice during the brief high-temperature window, then rapidly cooling to freeze in the desired strain state without prolonged exposure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method significantly reduces residual end-of-range disorder, improving device performance, yield, and reliability by achieving compressive strain and limiting strain relaxation, resulting in fewer dislocation lines per square centimeter.
Implementation Method 1
The PMOS region is implanted on at least opposing sides of the gate stack using implant conditions comprising at least one compressive strain inducing specie selected from Ge, Sn and Pb
Implementation Method 2
The wafer is then annealed using annealing conditions comprising a peak anneal temperature of between 1050° C. and 1400° C. and an anneal time at the peak temperature of ≦10 seconds, wherein the amorphous region recrystallizes by SPE
Implementation Method 3
the associated annealing process is typically a relatively long processing time, such as on the order of several minutes, or more
Data Source
AI summary
An integrated circuit (IC) includes a plurality of compressively strained PMOS transistors. The IC includes a substrate having a semiconductor surface. A gate stack is formed in or on the semiconductor surface and includes a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region is opposing sides of the gate stack. At least one compressive strain inducing region including at least one specie selected from Ge, Sn and Pb is located in at least a portion of the source and drain regions of the PMOS transistors, wherein the strain inducing region provides ≦1010 dislocation lines/cm2 and an active concentration of the compressive strain inducing specie that is above a solid solubility limit for the compressive strain inducing specie in the compressive strain inducing region. A method for forming compressively strained PMOS transistors includes implanting on at least opposing sides of the gate stack using at least one compressive strain inducing specie selected from Ge, Sn and Pb at a dose ≧1×1015 cm−2, at an implantation temperature during implanting in a temperature range ≦273 K, wherein the implant conditions are sufficient to form an amorphous region. The wafer is annealed using annealing conditions including a peak anneal temperature of between 1050° C. and 1400° C. and an anneal time at the peak temperature of ≦10 seconds, wherein the amorphous region recrystallizes by solid phase epitaxy (SPE).