III-V n-MOS Transistors with Strained Source Drain Regions
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Solution Overview
Problem
Current semiconductor devices face limitations in enhancing carrier mobility in channel regions, particularly in n-MOS transistors, due to insufficient strain application, which restricts the drive current and overall performance.
Innovation Solution
The implementation of III-V replacement channel regions and source/drain regions with a lattice mismatch to induce uniaxial tensile strain, achieved by epitaxially growing III-V semiconductor materials with specific lattice constants, thereby increasing electron mobility in n-MOS devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniaxial tensile strain is applied to the channel region to increase electron mobility, then drive current is improved, but excessive defects may be introduced
Solution Approach 1:
The patent changes the physical state and structural parameters of the channel region by introducing controlled uniaxial tensile strain through lattice mismatch. By carefully selecting materials with specific lattice constants and controlling the degree of mismatch, the patent optimizes electron mobility while preventing excessive defect formation. This involves adjusting composition ratios, layer thicknesses, and strain magnitudes to achieve the desired balance between performance improvement and structural integrity.
Solution Approach 2:
The patent employs composite material structures combining different III-V semiconductor materials (such as InGaAs, InAlAs, GaAs) with carefully engineered lattice constants. These composite structures create controlled strain fields in the channel region through lattice mismatch, enabling enhanced electron mobility. The multi-material approach allows independent optimization of each layer's properties to achieve both high mobility and low defect density.
2Reliability
If III-V replacement channel regions are implemented to enhance carrier mobility, then drive current increases, but device complexity increases
Solution Approach 1:
The patent segments the transistor structure into distinct functional regions with specific materials: III-V replacement channel region, source/drain regions, and barrier layers. Each segment is optimized for its specific function, with the channel region engineered for high carrier mobility through controlled strain, while other regions handle carrier injection and confinement. This segmentation allows independent optimization of each component without compromising overall device performance.
Solution Approach 2:
The patent introduces intermediary barrier layers and transition regions between the III-V channel and silicon substrate or other materials. These intermediary structures mediate the lattice mismatch and strain distribution, enabling the III-V channel to achieve high mobility while maintaining compatibility with the underlying substrate and reducing overall device complexity through standardized interface designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively enhances electron mobility in n-MOS transistors by generating targeted strain fields, improving carrier mobility and drive current without introducing excessive defects, thus optimizing transistor performance.
Implementation Method 1
III-V replacement source/drain (S/D) regions with a lattice mismatch to induce uniaxial tensile strain
Implementation Method 2
induce uniaxial tensile strain, achieved by epitaxially growing III-V semiconductor materials with specific lattice constants, thereby increasing electron mobility
Implementation Method 3
achieved by epitaxially growing III-V semiconductor materials with specific lattice constants
Data Source
Figure 1A~1C
Figure 2A~2B
Figure 3A~3B
AI summary
An n-MOS transistor device and method for forming such a device are disclosed. The n- MOS transistor device comprises a semiconductor substrate with one or more replacement active regions formed above the substrate. The replacement active regions comprise a first III-V semiconductor material. A gate structure is formed above the replacement active regions. Source/Drain (S/D) recesses are formed in the replacement active region adjacent to the gate structure. Replacement S/D regions are formed in the S/D recesses and comprise a second III-V semiconductor material having a lattice constant that is smaller than the lattice constant of the first III-V semiconductor material. The smaller lattice constant of the second III-V material induces a uniaxial-strain on the channel formed from the first III-V material. The uniaxial strain in the channel improves carrier mobility in the n-MOS device.