Strained Source/Drain Extensions for p-FET Carrier Mobility
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Solution Overview
Problem
Scaling down semiconductor devices to smaller technology nodes poses challenges in achieving enhanced carrier mobility for p-type field effect transistors due to difficulties in delivering strain to the channel region, leading to device instability and potential failure.
Innovation Solution
A method for fabricating a p-type field effect transistor with a strained source/drain structure involves forming recess cavities in the substrate, selectively growing silicon germanium within these cavities, and using thermal processes to drive boron into the active regions, thereby creating strained source/drain extensions that deliver strain to the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strained materials are used in source/drain recess cavities to enhance carrier mobility, then device performance is improved, but it becomes difficult to deliver sufficient strain into the channel region of p-type field effect transistors at scaled dimensions
Solution Approach 1:
The patent extends the strained source/drain structure into the third dimension by forming source/drain extensions that protrude into the channel region from below the substrate surface. This vertical extension allows strain to be delivered into the channel region at scaled gate lengths where conventional planar strained source/drain structures fail to provide sufficient strain.
Solution Approach 2:
The strained source/drain extensions are formed by nesting multiple structures: recess cavities are formed in the substrate, strained silicon germanium is selectively grown within these cavities, and then source/drain extensions protrude from the cavities into the channel region. This nested configuration allows the strained material to be positioned precisely where needed to deliver strain into the channel.
2Area of moving object
If gate length and spacing between devices are decreased to scale down the semiconductor device, then device density is improved, but the ability to deliver strain into the channel region deteriorates
Solution Approach 1:
By forming source/drain extensions that protrude vertically into the channel region from below the substrate surface, the patent delivers strain into the channel region without requiring increased lateral spacing between devices. This vertical dimension allows strain delivery at scaled device dimensions where conventional lateral approaches fail.
Solution Approach 2:
The strained source/drain extensions are selectively formed only in regions where strain delivery is needed, with the extensions protruding into the channel region adjacent to the gate electrode. This localized strain delivery maintains carrier mobility enhancement even as overall device spacing is reduced for higher density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier mobility and improves device performance by effectively introducing strain into the channel region of the p-type field effect transistor, stabilizing the device and increasing its yield.
Implementation Method 1
selectively growing silicon germanium within these cavities
Implementation Method 2
using thermal processes to drive boron into the active regions
Implementation Method 3
strained materials in source/drain (S/D) recess cavities of the MOSFET utilizing selectively grown silicon germanium (SiGe) may be used to enhance carrier mobility
Data Source
AI summary
A field effect transistor includes a substrate and spacers over the substrate. The field effect transistor includes a channel recess cavity between the spacers, wherein a bottom-most surface of the channel recess cavity is parallel to the substrate top surface. The field effect transistor includes a gate stack, wherein the gate stack includes a bottom portion in the channel recess cavity and a top portion outside the channel recess cavity, the gate stack further includes a gate dielectric layer extending from the channel recess cavity along sidewalls of each of the pair of spacers, and the gate dielectric layer directly contacts the substrate below substrate top surface. The field effect transistor includes a strained source/drain (S/D) below the substrate top surface, wherein the strained S/D extends below the gate stack. The field effect transistor further includes a source/drain (S/D) extension substantially conformably surrounding the strained S/D.