Semiconductor Source/Drain Stack With Strain and Bottom Isolation
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Solution Overview
Problem
Current semiconductor technologies face challenges in scaling FET devices to smaller dimensions while maintaining enhanced carrier mobility and bottom isolation for both nFET and pFET devices, particularly as the industry moves towards the 7-nm technology node and beyond.
Innovation Solution
The fabrication of semiconductor structures involves forming bottom source/drain regions with compressive pFET epitaxy and top source/drain regions with tensile nFET epitaxy, using sacrificial epitaxial layers and dielectric layers to enhance carrier mobility and achieve bottom isolation, with specific processes including etching, epitaxial growth, and sacrificial layer removal to create air gaps and improve epitaxial quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FET devices are scaled to smaller dimensions to increase device width per footprint area, then integration density improves, but maintaining enhanced carrier mobility and bottom isolation becomes difficult
Solution Approach 1:
The source/drain structure is segmented into multiple discrete layers (bottom source/drain region, middle source/drain region, top source/drain region) separated by dielectric layers. This segmentation allows independent optimization of each layer for carrier mobility enhancement while maintaining bottom isolation, resolving the contradiction between scaling for higher density and maintaining reliability.
Solution Approach 2:
The patent transitions from planar FET structures to three-dimensional stacked nanosheet FET structures. By stacking multiple nanosheet channels vertically, the effective channel width increases without increasing footprint area, enabling continued scaling while maintaining carrier mobility through the layered source/drain configuration.
2Reliability
If bottom source/drain regions are formed with compressive pFET epitaxy and top source/drain regions with tensile nFET epitaxy, then carrier mobility is enhanced, but process complexity increases
Solution Approach 1:
Different epitaxial conditions are applied to different regions: compressive pFET epitaxy for bottom source/drain regions and tensile nFET epitaxy for top source/drain regions. Each region receives locally optimized conditions for its specific device type, enhancing carrier mobility while the modular layered structure keeps the overall process manageable.
Solution Approach 2:
Sacrificial epitaxial layers are grown in advance before the actual source/drain regions. These sacrificial layers facilitate the subsequent formation of the strained source/drain regions and are selectively removed to create air gaps, simplifying the overall process by pre-positioning materials that will define the final structure.
3Reliability
If sacrificial epitaxial layers are used and selectively removed to create air gaps, then bottom isolation is achieved, but manufacturing steps increase
Solution Approach 1:
Sacrificial epitaxial layers serve as intermediary materials that facilitate the creation of air gaps for bottom isolation. These temporary structures are grown, used to define the source/drain regions, and then selectively removed to create the isolation gaps. The intermediary layers enable bottom isolation without requiring direct etching of the substrate, streamlining the process.
Solution Approach 2:
The sacrificial epitaxial layers are temporarily created and then selectively discarded through removal to form air gaps. This discarding of the sacrificial material achieves the desired bottom isolation structure. The process recovers the substrate surface in controlled areas, enabling subsequent processing steps while maintaining isolation where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in semiconductor structures with enhanced carrier mobility and effective bottom isolation for both nFET and pFET devices, enabling improved performance and scalability in advanced technology nodes.
Implementation Method 1
bottom source/drain region comprises a compressive pFET epitaxy and the top source/drain region comprises a tensile nFET epitaxy
Implementation Method 2
growing a first sacrificial epitaxial layer in the channel, growing a bottom source/drain region in the channel on the first sacrificial epitaxial layer
Data Source
AI summary
Illustrative embodiments provide techniques for fabricating semiconductor structures having bottom isolation and enhanced carrier mobility for both nFET and pFET devices. For example, in one illustrative embodiment, a semiconductor structure includes a semiconductor substrate, a first dielectric layer disposed on the semiconductor substrate, a bottom source/drain region disposed on the first dielectric layer and isolated from the semiconductor substrate by the first dielectric layer, a second dielectric layer disposed on the bottom source/drain region and a top source/drain region disposed on the second dielectric layer and isolated from the bottom source/drain region by the second dielectric layer. The bottom source/drain region comprises a compressive pFET epitaxy and the top source/drain region comprises a tensile nFET epitaxy.