Strained Source/Drain Tip Control via Three-Step Etching
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Solution Overview
Problem
Conventional methods for fabricating strained source/drain features in FinFETs fail to adequately control the depth and proximity of the tip of the strained source/drain feature, leading to increased drain-induced barrier lowering (DIBL) and compromised short channel control, despite efforts to reduce resistance and enhance carrier mobility.
Innovation Solution
A three-step etching process involving a first anisotropic etch, an isotropic etch, and a second anisotropic etch is employed to precisely control the location of the tip of the strained source/drain feature, with the tip positioned near the top of the fin and the bottom portion spaced further from the gate stack, resulting in a candle light bulb-shaped cross-section that reduces resistance and DIBL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to fabricate strained source/drain features, then manufacturing simplicity is maintained, but the depth and proximity of the tip cannot be adequately controlled, leading to increased DIBL and compromised short channel control
Solution Approach 1:
The etching process is divided into three distinct anisotropic etching steps, each targeting specific portions of the source/drain region. This segmentation allows independent control of tip depth, tip proximity, and bottom portion depth, resolving the contradiction by breaking down the complex control requirements into manageable sequential operations
Solution Approach 2:
The first anisotropic etching step preliminarily defines the tip depth and tip proximity parameters before subsequent etching steps modify the bottom portion. This preliminary action establishes a controlled foundation that prevents over-etching and ensures precise final dimensions, addressing the precision requirement while maintaining process structure
2Reliability
If the tip of the strained source/drain feature is positioned deeper to reduce resistance, then electrical conductivity improves, but DIBL increases and short channel control deteriorates
Solution Approach 1:
The etching process applies different depths to different portions of the source/drain feature: the tip is etched to a first depth optimized for conductivity, while the bottom portion is etched to a second depth that maintains proper spacing from the channel. This local differentiation resolves the contradiction by optimizing each region's depth for its specific function
Solution Approach 2:
The process independently controls multiple depth parameters (tip depth, tip proximity, bottom portion depth) through separate etching steps. By changing and optimizing each parameter independently, the process achieves the optimal balance between conductivity (requiring deeper tip) and short channel control (requiring controlled bottom depth)
3Reliability
If the bottom portion of the strained source/drain feature is positioned closer to the gate stack to reduce resistance, then electrical conductivity improves, but DIBL increases
Solution Approach 1:
The process differentiates between tip region etching (for conductivity) and bottom portion etching (for spacing control). The bottom portion is selectively etched to a controlled depth that maintains optimal spacing from the channel, preventing DIBL while the tip is optimized for electrical connection
Solution Approach 2:
The process independently adjusts the depth of the bottom portion relative to the tip depth through the second anisotropic etching step. This separate parameter control allows optimization of conductivity at the tip while maintaining appropriate spacing at the bottom to minimize DIBL
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed method effectively reduces channel resistance and DIBL, thereby improving FinFET operation and short channel control by optimizing the profile of the strained source/drain features.
Implementation Method 1
A three-step etching process involving a first anisotropic etch, an isotropic etch, and a second anisotropic etch is employed to precisely control the location of the tip
Implementation Method 2
A three-step etching process involving a first anisotropic etch, an isotropic etch, and a second anisotropic etch is employed to precisely control the location of the tip
Data Source
AI summary
Source and drain formation techniques are disclosed herein. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin while a bottom portion of the source/drain recess is spaced a distance from a gate footing. The source/drain recess is filled with an epitaxial semiconductor material.