Strained Source/Drain Trenches via Two-Step Etching
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Solution Overview
Problem
Conventional etching processes for forming trenches in semiconductor devices result in increased tensile stress and undesirable undercutting of substrate silicon, leading to short channel effects and erosion of overlying structures, which compromises the performance of transistor devices.
Innovation Solution
A two-step Br-based etching process is employed, with the first step including nitrogen as an etching gas and the second step excluding nitrogen, followed by an etch chemistry involving F and Cl, to selectively etch silicon without attacking silicon nitride sidewall spacers, thereby controlling the undercut and maintaining structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If extended isotropic etch times are used to increase tensile stress and lateral encroachment, then tensile stress level is improved, but undercut of the self-aligned masking structure is increased causing attack and erosion of overlying structures
Solution Approach 1:
The etching process is divided into multiple sequential steps with different chemistries and parameters. The first step uses CF4/HBr/HeO2 to create initial undercut, the second step uses NF3 to reduce further undercut, and the third step uses CF4/HBr to complete the etch. This segmentation allows control of tensile stress while limiting damage to masking structures.
Solution Approach 2:
The patent changes etching parameters including gas composition (CF4/HBr/HeO2, NF3, CF4/HBr), power levels (50-200W), pressure (10-100mTorr), and temperature to optimize the balance between generating tensile stress and controlling undercut. By adjusting these parameters across multiple steps, both stress and precision requirements are met.
2Reliability
If aggressive isotropic etch processes are used to produce increased tensile stress, then hole mobility is improved, but attack and erosion of sidewall spacers occurs causing pull-back of opening edges
Solution Approach 1:
The etching process applies different local conditions at different stages: initial aggressive etching where spacers are intact provides stress, followed by milder etching to complete the opening. The selective use of NF3 in the second step provides a gentler chemistry that continues etching without attacking the already-weakened spacer regions, maintaining spacer integrity while achieving the desired stress.
Solution Approach 2:
The first etch step performs preliminary undercutting and stress generation while the sidewall spacers are still structurally sound and可以提供 protection. This preliminary action establishes the tensile stress foundation before the spacers become vulnerable in subsequent steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances tensile stress in the trenches while preventing the pull-back of edges and maintaining the integrity of sidewall spacers, resulting in improved Idsat performance and reduced short channel effects.
Implementation Method 1
etching the silicon substrate by performing a plurality of Br-based etch processes that selectively etch silicon and not SiN
Implementation Method 2
produce an increased tensile stress, as this improves hole mobility in the formed devices
Data Source
AI summary
A semiconductor device is formed by a multi-step etching process that produces trench openings in a silicon substrate immediately adjacent transistor gate structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the transistor structure and forms the openings. The openings are bounded by upper surfaces that extend downwardly from the substrate surface and are substantially vertical, and lower surfaces that bulge outwardly from the upper vertical sections and undercut the transistor structure. The openings may be filled with a suitable source/drain material to produce SSD transistors with desirable Idsat characteristics.