Strained Semiconductor Layer Integration for N and P Type Devices
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Solution Overview
Problem
In semiconductor processing, integrating n-type and p-type devices on the same substrate is challenging due to performance degradation, as scaling down device sizes degrades mobility, and different crystal orientations and straining methods favor one type of device over the other, making it difficult to achieve high performance for both types simultaneously.
Innovation Solution
A biaxially tensile strained semiconductor layer with a (100) surface crystal orientation is used for both n-type and p-type devices, with the semiconductor layer being thickened and relaxed in regions where p-type devices are formed to reduce intrinsic tension, allowing for improved performance of both device types by maintaining tensile strain in n-type regions and relaxing it in p-type regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the semiconductor layer is thickened and relaxed in p-type device regions, then p-type device performance is improved, but the intrinsic tension in the semiconductor layer is reduced
Solution Approach 1:
The relaxation of intrinsic tension is performed locally only in regions where p-type devices are to be formed, not uniformly across the entire semiconductor layer. This is accomplished through selective epitaxial growth that thickens the semiconductor layer in specific p-type device regions, thereby relaxing the tension only where needed while preserving the beneficial tensile strain in n-type device regions.
2Productivity
If device sizes are scaled down to increase integration density, then productivity is improved, but carrier mobility degrades
Solution Approach 1:
The patent utilizes parameter changes by introducing and controlling strain in the semiconductor layer through selective relaxation. By adjusting the strain state (tensile in n-type regions, relaxed in p-type regions) and crystal orientation ((100) surface), the patent improves carrier mobility despite device scaling. This allows smaller device dimensions to be achieved while maintaining or enhancing mobility through the strain engineering approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of both n-type and p-type devices on the same substrate with improved performance for each type, utilizing optimal crystal orientations and strain levels to enhance carrier mobility without degrading the performance of either type.
Implementation Method 1
the silicon in which the devices are formed may be strained. For example, for n-type devices, the silicon may be tensile strained to improve mobility
Implementation Method 2
the semiconductor layer being thickened and relaxed in regions where p-type devices are formed to reduce intrinsic tension
Data Source
AI summary
Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region having a first conductivity type, forming an insulating layer overlying at least an active area of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material overlying at least a portion of the insulating layer.