Strained Semiconductor Layers for PMOS and NMOS Transistors
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Solution Overview
Problem
Current techniques for enhancing charge carrier mobility in transistors, such as strain engineering, face inefficiencies and increased complexity, particularly in forming strained layers for PMOS and NMOS transistors on thin SOI layers, where stress transfer is restricted, leading to reduced performance gains and complex process flows.
Innovation Solution
A method is introduced to form differently strained semiconductor layers for P-channel and N-channel transistors using a simplified process flow that omits hard masks for one type of transistor, allowing for efficient epitaxial growth and positioning of strained material close to the channel region, reducing process complexity and enabling effective strain induction in both fully and partially depleted transistor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external stress is applied to create strain in the channel region, then charge carrier mobility is improved, but the translation of external stress into strain is inefficient
Solution Approach 1:
The patent introduces embedded strain layers as intermediary structures between the channel region and external stress sources. These strain layers directly induce mechanical stress in the channel region through their inherent material properties, eliminating the inefficiency of external stress application. The strain layers act as mediators that convert material composition differences into controlled mechanical stress, achieving efficient stress translation without complex external apparatus.
Solution Approach 2:
The strain layers are formed during the epitaxial growth process before final device assembly, preliminarily establishing the stress state in the channel region. By incorporating strain-inducing materials (such as SiGe or SiC layers) during semiconductor layer formation, the desired mechanical stress is built into the device structure in advance, ensuring efficient stress translation is maintained throughout subsequent manufacturing and operation.
2Adaptability or versatility
If complex masking schemes are used to form strained layers for different transistor types, then selective strain induction is achieved, but process complexity increases
Solution Approach 1:
The patent applies different strain layer configurations to different transistor types based on their specific requirements. NMOS transistors receive tensile strain layers (e.g., SiGe) while PMOS transistors receive compressive strain layers (e.g., SiC), with each strain layer selectively positioned only where needed. This local differentiation achieves selective strain induction for optimized carrier mobility in each transistor type without requiring complex global masking schemes, as the strain application is inherently localized through targeted epitaxial growth.
Solution Approach 2:
The epitaxial growth process itself provides the selectivity mechanism through in-situ masking and selective growth conditions. The process automatically deposits strain layers only in designated regions based on precursor distribution and growth parameters, eliminating the need for separate photolithography masking steps. Each transistor type self-receives its appropriate strain layer through controlled local epitaxial conditions, reducing process complexity while maintaining selective strain induction capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of PMOS and NMOS transistors by efficiently forming strained layers with reduced process complexity, improving charge carrier mobility and transistor performance without the need for complex masking schemes, especially beneficial for advanced SOI transistors with thin active layers.
Implementation Method 1
creating tensile or compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively
Implementation Method 2
a first strained semiconductor material is epitaxially grown in the first recess and a second strained semiconductor material is epitaxially grown in the second recess
Data Source
AI summary
By omitting a growth mask or by omitting lithographical patterning processes for forming growth masks, a significant reduction in process complexity may be obtained for the formation of different strained semiconductor materials in different transistor types. Moreover, the formation of individually positioned semiconductor materials in different transistors may be accomplished on the basis of a differential disposable spacer approach, thereby combining high efficiency with low process complexity even for highly advanced SOI transistor devices.