Strained Semiconductor Device with Low-Temperature Anneal
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Solution Overview
Problem
Current semiconductor-on-insulator (SOI) technology faces challenges in achieving desired tensile strain in NFET devices due to high rapid thermal anneal temperatures, which cause carbon atoms to exit substitutional states, reducing or eliminating the desired tensile stress.
Innovation Solution
The method involves forming alternating semiconductor channel layers with silicon germanium for PFET and silicon for NFET devices, using in-situ boron-doped silicon germanium and phosphorus-doped silicon epitaxial growth for source and drain regions, and growing silicon carbide epitaxially for raised source and drain regions to provide compressive and tensile strain respectively, while performing thermal anneal at temperatures below 600°C to preserve carbon atoms in substitutional states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high-temperature rapid thermal anneal is used to form source and drain regions, then dopant activation and junction formation are improved, but carbon atoms exit substitutional states causing loss of tensile strain in NFET devices
Solution Approach 1:
The patent changes the temperature parameter from high-temperature rapid thermal anneal to low-temperature anneal (below 600°C) to preserve carbon atoms in substitutional states while still achieving adequate dopant activation through alternative mechanisms
Solution Approach 2:
The patent performs preliminary in-situ doped epitaxial growth to form source and drain regions with dopants already incorporated in the crystal lattice, eliminating the need for high-temperature anneal to activate dopants
2Manufacturing precision
If in-situ doped epitaxial growth is used to form source and drain regions, then dopant distribution and strain control are improved, but process complexity increases
Solution Approach 1:
The patent combines dopant incorporation and source/drain region formation into a single in-situ epitaxial growth step, achieving both dopant distribution and strain control simultaneously without requiring separate implantation and anneal steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively maintains carbon atoms in substitutional states, providing desired compressive strain for PFET and tensile strain for NFET devices, enhancing device performance without the need for high-temperature rapid thermal anneal, thus improving strain effectiveness in smaller processing nodes.
Implementation Method 1
using in-situ boron-doped silicon germanium and phosphorus-doped silicon epitaxial growth for source and drain regions
Implementation Method 2
performing a thermal anneal to form source and drain extension regions in the first and second semiconductor channel layers beneath the gates
Implementation Method 3
forming source and drain regions on opposing sides of the gate over the first semiconductor channel layer comprising the first semiconductor material and a first dopant to provide a compressive strain in the first semiconductor channel layer
Data Source
AI summary
A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal treatment to form source drain extension regions, to thereby preserve the strain-inducing material in desired substitutional states.