Strained Semiconductor Device PN Junction Leakage Reduction
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Solution Overview
Problem
Current semiconductor processes face significant current leakage issues due to the coincidence of the PN junction with the interface between the N-type substrate and the P-type epitaxy SiGe layer in strained S/D regions, particularly in PMOS transistors.
Innovation Solution
The method involves forming a substrate with a first semiconductor material and a second conductivity type semiconductor layer through selective epitaxy growth (SEG) with in-situ doping, followed by in-situ annealing to shift the PN junction away from the interface between the substrate and the epitaxial layer, reducing current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If selective epitaxy growth (SEG) is used to form strained S/D region, then carrier mobility is increased and S/D resistance is reduced, but current leakage through the PN junction occurs at the interface between substrate and epitaxy layer
Solution Approach 1:
The invention transitions from a two-dimensional interface problem to a three-dimensional spatial solution by forming a graded composition buffer layer with intermediate Ge concentration between the Si substrate and high-Ge strained S/D layer. This buffer layer creates a gradual transition zone that eliminates the sharp interface causing leakage, effectively adding a compositional dimension to solve the interface problem.
Solution Approach 2:
The invention changes the Ge concentration parameter gradually from 0% in the Si substrate to intermediate values in the buffer layer (e.g., 5-20% Ge), and finally to high values (e.g., 30-50% Ge) in the strained S/D layer. This parameter gradient approach eliminates the abrupt compositional change that causes misfit dislocation and current leakage.
2Reliability
If high Ge concentration is used in S/D region to increase strain, then carrier mobility improves, but misfit dislocation increases causing leakage
Solution Approach 1:
The invention implements a gradual parameter change by forming a buffer layer with intermediate Ge concentration (e.g., 5-20%) between the Si substrate (0% Ge) and the high-Ge strained S/D layer (30-50% Ge). This gradual parameter transition reduces lattice mismatch and minimizes misfit dislocation, maintaining compositional stability while enabling high strain in the final S/D region.
Solution Approach 2:
The buffer layer is formed as a preliminary structure before depositing the high-Ge strained S/D layer. This preliminary action of creating a graded composition buffer layer prepares the substrate to accommodate the high-Ge layer with reduced dislocation, preventing the harmful effects of abrupt interface formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces current leakage through the PN junction of the S/D region, enhancing the performance of strained semiconductor devices by optimizing the positioning of the PN junction.
Implementation Method 1
an epitaxial layer of a second conductivity type is formed through selective epitaxy growth (SEG) with in-situ doping
Implementation Method 2
in-situ annealing is then conducted to diffuse the dopant
Data Source
AI summary
A method for forming a strained semiconductor device is described. A substrate including a first semiconductor material and having a first conductivity type is provided. A semiconductor layer of a second conductivity type is formed contacting with the substrate, wherein the semiconductor layer includes the first semiconductor material and a second semiconductor material and has a dopant of the second conductivity type. In-situ annealing is then conducted to diffuse the dopant.