Strained Semiconductor Regions for RF Switch Performance
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Solution Overview
Problem
Existing RF switch transistor devices face limitations in improving Ron-Coff performance beyond channel length scaling, with previous attempts using expensive GaAs or SOS substrates that are not easily integrated with CMOS processing, limiting the integration of high-density logic and power amplifier devices on conventional silicon substrates.
Innovation Solution
The method involves fabricating integrated circuits with selectively strained semiconductor device regions by forming a substrate with a semiconductor layer over an insulator layer, selectively thinning and relaxing regions, and forming strained layers to achieve improved Ron-Coff performance, allowing for integration with conventional CMOS processing and enhanced device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If channel length is scaled down to improve Ron-Coff performance, then Ron decreases and Coff decreases, but manufacturing precision requirements increase and device reliability deteriorates due to trade-offs in continuous scaling
Solution Approach 1:
The patent changes the physical state and properties of the semiconductor layer by introducing strain through selective thinning and relaxed/strained layer formation. This transforms the conventional unstrained silicon layer into a strained semiconductor layer with modified electrical properties, enabling improved carrier mobility and performance without further scaling the channel length dimension.
Solution Approach 2:
The patent creates a composite structure consisting of multiple layers with different properties: the original semiconductor layer, selectively thinned regions, relaxed layers, and strained layers. This multi-layer composite architecture combines the benefits of conventional CMOS compatibility with enhanced device performance through controlled strain in specific regions.
2Reliability
If GaAs or SOS substrates are used to improve Ron-Coff performance, then device performance improves, but manufacturing cost increases significantly and integration with CMOS processing becomes difficult
Solution Approach 1:
The patent applies strain selectively to specific device regions rather than uniformly across the entire substrate. By using selective thinning and localized relaxed/strained layer formation, the patent creates regions with enhanced properties where needed while maintaining conventional unstrained regions for other devices, enabling mixed-signal integration with standard CMOS processes.
Solution Approach 2:
The patent segments the semiconductor layer into different regions with different thicknesses and strain states. The selective thinning process creates isolated regions that can be independently controlled, allowing some areas to have strained layers for high-performance RF switches while other areas maintain conventional structures for logic or other functions.
3Reliability
If selective thinning and strained layer formation are used to improve Ron-Coff performance, then Ron decreases by 1.3 to 1.8 times and sidewall junction capacitance decreases by 50%, but device complexity increases
Solution Approach 1:
The patent introduces relaxed layers as intermediary structures between the selectively thinned semiconductor layer and the strained layer. These relaxed layers serve as buffer zones that accommodate lattice mismatch and enable the formation of high-quality strained layers without defects, simplifying the overall fabrication process compared to direct strained layer formation on thinned regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces Ron by 1.3 to 1.8 times and sidewall junction capacitance by 50% compared to conventional RFSOI switch FET devices, achieving better on-off ratios and Ron performance while maintaining compatibility with CMOS processing, enabling fully-depleted switch FET devices with improved integration scalability.
Implementation Method 1
selectively forming a relaxed layer on the isolated semiconductor layer region
Implementation Method 2
selectively forming a strained layer on the relaxed layer
Data Source
AI summary
Integrated circuits and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes providing a substrate including a semiconductor layer over an insulator layer. The method includes selectively replacing portions of the semiconductor layer with insulator material to define an isolated semiconductor layer region. Further, the method includes selectively forming a relaxed layer on the isolated semiconductor layer region. Also, the method includes selectively forming a strained layer on the relaxed layer. The method forms a device over the strained layer.