Strained Semiconductor Spacer Fabrication Residue Removal
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Solution Overview
Problem
Traditional methods of forming spacers in semiconductor fabrication often leave undesired residue in recess regions, which can interfere with subsequent processing steps and affect device performance.
Innovation Solution
A method involving the formation of a gate stack with dummy spacers, recess regions, epi-growth of strained semiconductor material, and a series of dry etching processes to create multilayered spacers on the sidewalls, ensuring complete removal of spacer material from the recess regions and preventing residue formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional spacer formation methods are used, then the process is simple and fast, but spacer material residue remains in recess regions
Solution Approach 1:
The spacer formation process is divided into multiple sequential deposition steps creating distinct layers (first spacer layer, second spacer layer, third spacer layer) with different etch selectivities. Each layer can be selectively removed by targeted etching processes, enabling complete residue removal from recess regions while maintaining the desired spacer structure on sidewalls.
Solution Approach 2:
Different regions of the spacer structure are assigned different material compositions and properties. The first spacer layer has high etch selectivity for removing residue from recess regions, while subsequent layers provide structural integrity and final spacer functionality. This local differentiation allows selective removal of material from specific locations without affecting other regions.
2Manufacturing precision
If multiple dry etching processes are performed to remove residue, then spacer material is completely removed from recess regions, but processing time increases
Solution Approach 1:
The first spacer layer is deposited with specifically tailored etch selectivity characteristics before subsequent layers are added. This preliminary layer is designed to be preferentially removed by the first dry etching process, enabling residue removal from recess regions before the final spacer structure is completed. This preliminary action prevents residue formation rather than requiring extensive post-formation cleaning.
Solution Approach 2:
The etch selectivity parameters are optimized across different spacer layers and etching processes. By controlling deposition conditions and material composition, each layer exhibits distinct etch response characteristics. This allows the first etching process to selectively remove residue-containing material while preserving the functional spacer structure, reducing the need for multiple aggressive cleaning steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier mobility by creating a strained interface and eliminates spacer residue issues, improving the efficiency of semiconductor device fabrication and compatibility with CMOS processes.
Implementation Method 1
epi-growing a semiconductor material in the recess region, wherein the semiconductor material is different from the silicon substrate
Implementation Method 2
performing a first dry etching process to remove a portion of the second silicon oxide layer; performing a second dry etching process to remove a portion of the silicon nitride layer; and performing a third dry etching process to remove a portion of the first silicon oxide layer
Data Source
AI summary
The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack.