Strained Semiconductor Stress Sources for MOS Transistor Channel
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Solution Overview
Problem
The challenge in integrated circuit fabrication is to enhance charge carrier mobility in MOS transistors while avoiding the limitations of scaling down transistor dimensions, particularly in SOI devices where the thickness of the silicon layer restricts the efficiency of strained silicon/germanium material usage.
Innovation Solution
Positioning strained semiconductor material extremely close to the gate electrode, with minimal offset, to enhance stress transfer into the channel region, and using a recessed configuration with a stressed overlayer to achieve efficient strain induction, even in highly scaled SOI transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of substance
If strained semiconductor material is positioned far from the gate electrode, then material consumption is reduced, but strain transfer efficiency to the channel region decreases
Solution Approach 1:
The patent positions the strained semiconductor material extremely close to the gate electrode in the lateral dimension, with the material extending above the gate insulation layer in the vertical dimension. This spatial arrangement in multiple dimensions maximizes stress transfer to the channel region while minimizing material consumption.
Solution Approach 2:
The strained semiconductor material is positioned specifically in the region where stress transfer to the channel is most effective, rather than uniformly distributing material. The material is placed adjacent to the gate electrode where it can directly induce strain in the channel region through stress transfer.
2Speed
If transistor dimensions are scaled down, then operating speed increases, but charge carrier mobility decreases
Solution Approach 1:
The patent modifies the physical state of the semiconductor material by introducing strain through stressed layers. This changes the lattice structure parameters of the channel region, increasing charge carrier mobility without requiring further scaling of transistor dimensions.
Solution Approach 2:
The patent uses composite structures combining strained semiconductor material with the channel region. The strained material acts as a stress source that transfers mechanical stress to the channel, creating a composite system where the strained layer enhances carrier mobility in the unstrained channel region.
3Reliability
If strained silicon/germanium material is used in SOI devices, then charge carrier mobility increases, but the thickness of the silicon layer restricts material usage efficiency
Solution Approach 1:
In SOI devices with thin silicon layers, the patent positions the strained semiconductor material laterally adjacent to the gate electrode and allows it to extend vertically above the gate insulation layer. This vertical extension provides an additional dimension for stress transfer, compensating for the limited thickness of the silicon layer and maximizing the utility of the strained material.
Solution Approach 2:
The strained material is positioned specifically where it can most effectively influence the channel region despite the thin silicon layer. By concentrating the strained material in the critical stress transfer zone rather than attempting to strain the entire thin layer, the patent achieves high mobility enhancement with minimal material usage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases strain in the channel region, improving transistor performance by maintaining high strain levels without consuming precious strained material and reducing strain relaxation effects, thus enhancing the efficiency of strain generation in both SOI and bulk devices.
Implementation Method 1
Positioning strained semiconductor material extremely close to the gate electrode, with minimal offset, to enhance stress transfer into the channel region
Implementation Method 2
creating tensile or compressive stress in the vicinity of the channel region so as to produce a corresponding strain in the channel region
Data Source
AI summary
A strained semiconductor material may be positioned in close proximity to the channel region of a transistor, such as an SOI transistor, while reducing or avoiding undue relaxation effects of metal silicides and extension implantations, thereby providing enhanced efficiency for the strain generation.