Strained Si on Si:C-OI Islands for nFET pFET Stress
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Solution Overview
Problem
Current methods for creating tensile and compressive stresses in semiconductor devices, such as nFETs and pFETs, are complex and costly, often requiring additional materials and high Ge% content, which is difficult to implement and can be detrimental to pFET performance, while existing stress application methods result in moderate stress levels and surface roughness issues.
Innovation Solution
The method involves forming shallow trench isolation (STI) in a substrate with different materials, such as Ge and Si:C, and thermally annealing these materials to create relaxed SiGe and Si:C islands, allowing for the growth of strained Si layers that apply tensile and compressive stresses to nFET and pFET channels, respectively, using high temperature stable amorphous materials like SiO2 to facilitate relaxation and improve device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high Ge% content is used to create compressive stress in pFET channels, then device performance is improved, but manufacturing complexity increases and surface roughness deteriorates
Solution Approach 1:
The patent changes the material composition parameter by using Si:C (silicon carbide) instead of high Ge% (germanium) content. This parameter substitution achieves the desired compressive stress effect while avoiding the manufacturing complexities and surface roughness issues associated with high Ge% materials. The Si:C layer provides equivalent stress benefits with improved manufacturability.
2Reliability
If SiGe is used to apply tensile stress to nFET channels, then device performance is improved, but the stress level is limited and manufacturing becomes more complex
Solution Approach 1:
The patent replaces expensive and complex SiGe materials with a more manufacturable alternative. Si:C (silicon carbide) is used to achieve the desired stress effects without the high cost and manufacturing complexity associated with SiGe processes. This substitution maintains performance benefits while improving ease of manufacture and reducing production costs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of semiconductor devices with enhanced performance by applying desired stresses without the need for high Ge% content, reducing defect issues and improving mobility, while maintaining cost-effectiveness and simplifying the manufacturing process.
Implementation Method 1
A method of manufacturing a structure is provided. Shallow trench isolation (STI) is formed in a substrate and a first material and a second material are provided on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process
Data Source
AI summary
A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.