Strained Si and SiGe CMOS Device Surface Leveling
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Solution Overview
Problem
Current CMOS devices with strained Si and SiGe layers face challenges in achieving sufficient carrier mobility and accurate contact hole formation due to step generation between NMOS and PMOS regions, leading to reduced device performance and accuracy in manufacturing.
Innovation Solution
A semiconductor device and manufacturing method that utilize semiconductor layers with specific plane orientations for NMOS and PMOS regions, where the first semiconductor layer has a different plane orientation than the substrate and the second semiconductor layer maintains the substrate's orientation, enhancing carrier mobility and preventing step generation by epitaxial growth and controlled layer removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a relaxed SiGe layer and strained Si layer are laminatingly formed and the strained SiGe layer is removed to expose the strained Si layer in the NMOS region, then the carrier mobility in NMOS is enhanced, but a step is generated between NMOS and PMOS regions
Solution Approach 1:
The patent applies local quality by forming a strained SiGe layer selectively in the PMOS region and a strained Si layer selectively in the NMOS region. This allows each region to have the optimal material composition for its specific function: SiGe for PMOS to enhance hole mobility and Si for NMOS to enhance electron mobility, while maintaining different thicknesses to achieve surface leveling.
Solution Approach 2:
The patent changes the material composition parameter (Si vs SiGe) and layer thickness parameter between NMOS and PMOS regions. By controlling the Ge concentration and layer thickness locally in each region, the patent achieves both high carrier mobility and surface leveling without generating steps.
2Ease of manufacture
If the strained SiGe layer and strained Si layer are removed to expose the strained Si layer, then the channel region can be formed, but the step generation worsens the contact hole formation accuracy
Solution Approach 1:
The patent performs preliminary action by forming the strained SiGe layer in the PMOS region and strained Si layer in the NMOS region with controlled thicknesses before removing unnecessary layers. This preliminary structuring ensures that when layers are removed, the surface levels align, enabling accurate contact hole formation without steps.
3Productivity
If simple miniaturization is used to enhance drive capability, then device size is reduced, but leak current and short channel effect increase
Solution Approach 1:
The patent uses composite materials by combining Si and SiGe layers with specific strain configurations. The strained Si layer in NMOS and strained SiGe layer in PMOS create tensile and compressive strains respectively, enhancing carrier mobility and drive capability without requiring further miniaturization, thus avoiding increased leak current and short channel effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier mobility in both NMOS and PMOS regions, improving CMOS device performance and enabling high-accuracy contact hole formation, thus increasing yield.
Implementation Method 1
a relaxed SiGe layer, a strained Si layer and a strained SiGe layer are laminatingly formed on an Si substrate
Implementation Method 2
a strained Si layer in a tension-strained state is formed thereon, and a channel region is formed in the strained Si layer, the carrier mobility (electron mobility) in the channel region is enhanced
Data Source
AI summary
A semiconductor device including an NMOS region and a PMOS region in the same substrate, wherein the semiconductor device includes a strained Si layer which is provided on the substrate in the NMOS region and in which the surface has a plane orientation different from that of the substrate, and a strained SiGe layer which is provided on the substrate in the PMOS region and which is composed of a stained layer having the same plane orientation as that of the surface of the substrate; and a method of manufacturing the same.