Strained SiGe Cavities for Uniform Channel Strain
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Solution Overview
Problem
Strained materials fail to consistently deliver a given amount of strain to the channel region of field-effect transistors, leading to device instability and performance issues, particularly as gate length and spacing decrease in CMOS fabrication.
Innovation Solution
A method involving the formation of cavities in the semiconductor device that extend through the germanium channel and into the silicon substrate, followed by epitaxial growth of a strained SiGe layer to uniformly distribute strain, using LPCVD processes to ensure consistent strain delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strained materials are used in source and drain recess cavities to enhance carrier mobility, then device performance is improved, but the strain distribution becomes non-uniform leading to device instability and failure
Solution Approach 1:
The source and drain regions are segmented into multiple recess cavities at different depths within the channel region. Each cavity is filled with strained material independently, allowing precise control over strain distribution. This segmentation enables the strained material to be delivered uniformly to specific locations without affecting adjacent regions, resolving the non-uniform strain distribution problem.
Solution Approach 2:
Different regions of the channel are provided with different strain characteristics by creating recess cavities at specific locations (source and drain regions) with controlled depths and dimensions. The strained material is selectively deposited only in these localized cavities, ensuring that strain is applied precisely where needed while maintaining uniform distribution within each cavity. This local quality approach prevents the strain non-uniformity that leads to device instability.
2Productivity
If gate length and spacing between devices are decreased to scale down the semiconductor device, then device density is improved, but strain delivery to channel region becomes insufficient
Solution Approach 1:
Instead of relying solely on lateral strain delivery in the plane of the channel, the invention introduces a vertical dimension by creating recess cavities that extend downward from the channel region. The strained material is deposited in these vertical cavities, providing strain delivery in the depth direction. This dimensional transition ensures sufficient strain delivery even when gate length is reduced, maintaining carrier mobility enhancement while achieving higher device density.
Solution Approach 2:
The recess cavities are formed and pre-filled with strained material before the final device assembly and operation. This preliminary action ensures that the strain is already in place and uniformly distributed in the channel region before the device is put into operation. By preparing the strain structure in advance, the invention ensures consistent strain delivery even in scaled-down devices with reduced gate lengths and spacing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier mobility and device performance by ensuring a uniform distribution of strain in the channel region, thereby improving the on-current and stability of semiconductor devices.
Implementation Method 1
epitaxial growth of a strained SiGe layer to uniformly distribute strain
Data Source
AI summary
A method of fabricating a field effect transistor (FET) includes forming a channel portion over a first surface of a substrate, wherein the channel portion comprises germanium and defines a second surface above the first surface. The method further includes forming cavities that extend through the channel portion and into the substrate. The method further includes epitaxially-growing a strained material in the cavities, wherein the strained material comprises SiGe, Ge, Si, SiC, GeSn, SiGeSn, SiSn or a III-V material.