Fully Strained SiGe Channel Structure With Defect-Controlled Epitaxy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Fully strained channels in CMOS devices are prone to epitaxial growth defects and structural deformations due to processing stress, which can offset mobility benefits, particularly in p-type field effect transistors with larger Si to SiGe lattice mismatch.
Innovation Solution
A fabrication method involving multiple surface pre-clean treatment cycles with nitrogen trifluoride and ammonia plasma, followed by thermal treatment, and SiGe epitaxial growth with a Si seed layer or Si:C seed layer, is used to mitigate defects and deformations, ensuring a substantially defect-free and vertically oriented SiGe channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SiGe epitaxial growth is performed to form a fully strained channel, then carrier mobility is improved and channel resistance is reduced, but epitaxial growth defects and structural deformations occur due to processing stress and lattice mismatch
Solution Approach 1:
The patent applies preliminary action by performing multiple surface pre-clean treatment cycles with nitrogen trifluoride and ammonia plasma, followed by thermal treatment, before SiGe epitaxial growth. This preparatory surface treatment mitigates epitaxial growth defects and structural deformations by removing contaminants and preparing the substrate surface, thereby enabling defect-free fully strained SiGe channel formation while maintaining carrier mobility improvements
Solution Approach 2:
The patent employs parameter changes by optimizing the epitaxial growth conditions including using a Si seed layer or Si:C seed layer, controlling the SiGe composition gradient, and adjusting thermal treatment parameters. These parameter optimizations reduce lattice mismatch effects and processing stress, preventing epitaxial growth defects while maintaining the fully strained channel structure for high carrier mobility
2Manufacturing precision
If multiple surface pre-clean treatment cycles are performed, then epitaxial growth defects are reduced, but processing time and complexity increase
Solution Approach 1:
The patent consolidates multiple surface pre-clean treatment cycles into a standardized preliminary processing sequence performed before epitaxial growth. By systematically applying nitrogen trifluoride plasma, ammonia plasma, and thermal treatment as preparatory steps, the method achieves defect-free channels while minimizing redundant processing time through optimized treatment durations and sequences
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces epitaxial growth defects and structural deformations, maintaining strain-induced drive current enhancement and carrier mobility improvements in CMOS devices, particularly for p-type transistors, while ensuring the integrity of the channel region.
Implementation Method 1
exposing the well to a plasma, performing an anneal
Implementation Method 2
exposing the well to a plasma, performing an anneal
Implementation Method 3
exposing the well to a plasma, performing an anneal
Implementation Method 4
SiGe epitaxial growth with a Si seed layer or Si:C seed layer
Data Source
AI summary
The present disclosure describes an exemplary fin structure formed on a substrate. The disclosed fin structure comprises an n-type doped region formed on a top portion of the substrate, a silicon epitaxial layer on the n-type doped region, and an epitaxial stack on the silicon epitaxial layer, wherein the epitaxial stack comprises a silicon-based seed layer in physical contact with the silicon epitaxial layer. The fin structure can further comprise a liner surrounding the n-type doped region, and a dielectric surrounding the liner.