Strained SiGe Channel FETs with Segmented Isolation
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Solution Overview
Problem
Shallow trench isolation in semiconductor fabrication can relax the strain in SiGe channels of p-type field-effect transistors, leading to reduced device performance.
Innovation Solution
A method is developed to form a device structure using a silicon-on-insulator substrate with a strained channel and isolation regions, where a portion of the device layer between the isolation region and the channel is under less strain than the channel, using epitaxial semiconductor layers and thermal processes to maintain compressive strain in the channel, preventing strain relaxation during isolation formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shallow trench isolation is formed to isolate neighboring field-effect transistors, then electrical isolation between devices is improved, but the strain in the SiGe channel is relaxed leading to reduced carrier mobility
Solution Approach 1:
The device layer is segmented into multiple regions with different strain states: a first region under the gate structure containing the strained channel, and a second region serving as the isolation structure. This segmentation allows the channel region to maintain high strain for carrier mobility while the isolation region provides electrical separation between devices.
Solution Approach 2:
Different regions of the device layer are assigned different strain characteristics: the channel region under the gate is maintained under high compressive strain to maximize hole carrier mobility, while the isolation region is formed with reduced strain. This local differentiation of strain quality enables simultaneous optimization of device performance and electrical isolation.
2Reliability
If the device layer is fully utilized for isolation to improve device separation, then electrical isolation between transistors is enhanced, but the strain in the channel is reduced compromising device performance
Solution Approach 1:
The device layer is divided into functionally distinct segments: a channel-forming first region that remains under the gate structure and maintains high compressive strain, and an isolation-forming second region that is removed or modified to provide electrical isolation. This segmentation enables independent optimization of strain preservation in the channel and isolation effectiveness between devices.
Solution Approach 2:
The strain state is locally optimized for different functions: the first region under the gate is maintained with high compressive strain to ensure superior hole carrier mobility and device performance, while the second region is selectively removed or relaxed to provide effective electrical isolation. This local quality differentiation resolves the conflict between isolation and strain maintenance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances hole carrier mobility in p-type field-effect transistors by maintaining strain in the channel, improving device performance without reducing carrier mobility due to isolation formation.
Implementation Method 1
the channel comprised of a semiconductor material under strain
Implementation Method 2
using epitaxial semiconductor layers and thermal processes to maintain compressive strain in the channel
Implementation Method 3
using epitaxial semiconductor layers and thermal processes to maintain compressive strain in the channel
Data Source
AI summary
Device structures for a field-effect transistor and methods of forming such device structures using a device layer of a silicon-on-insulator substrate. A channel and an isolation region are formed in the device layer. The channel is located beneath a gate structure is formed on the device layer and is comprised of a semiconductor material under strain. A portion of the device layer is located between the first isolation region and the channel. The portion of the device layer is under a strain that is less than the strain in the semiconductor material of the channel.