Strained Si and SiGe CMOS Transistors for Mobility
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Solution Overview
Problem
In CMOS circuits, achieving high mobility for both nMISFET and pMISFET while minimizing the short channel effect and avoiding the complexity of inclining device directions and surface orientations is challenging, particularly in multi-gate structures where uniform strain application is difficult and leads to area penalties and circuit design complications.
Innovation Solution
A semiconductor device is developed where an n-channel MIS transistor uses an Si layer with uniaxial tensile strain and a p-channel MIS transistor uses an SiGe or Ge layer with uniaxial compressive strain, both aligned in the same direction, allowing for improved mobility without altering device orientations, and a manufacturing method involving epitaxial growth and oxidation to achieve these strains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device directions of nMISFET and pMISFET are inclined by 45° to optimize plane orientations and strains, then mobility of both devices is improved, but area penalty and circuit design complexity increase
Solution Approach 1:
The patent changes the material parameter (using SiGe for pMISFET channel instead of Si) to alter the strain characteristics. This allows the pMISFET to achieve high mobility with compressive strain in the same current direction as the nMISFET, eliminating the need for 45° device direction inclination and resolving the circuit design complexity issue while maintaining mobility improvement
Solution Approach 2:
The patent applies different material compositions locally: Si for nMISFET channel and SiGe for pMISFET channel. This local differentiation allows each device to have optimized strain characteristics (tensile for nMISFET, compressive for pMISFET) while sharing the same current direction, thus avoiding area penalty and design complexity
2Ease of manufacture
If a single semiconductor layer is used to uniformly apply strain, then fabrication scalability is improved, but uniform application of optimum strain to both nMISFET and pMISFET becomes difficult
Solution Approach 1:
The patent uses composite materials with different compositions (Si and SiGe) for the channels of nMISFET and pMISFET respectively. This allows each material to provide the appropriate strain type (tensile for Si, compressive for SiGe) needed by each device type, achieving uniform optimum strain application while maintaining fabrication scalability through a unified process approach
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances mobility for both nMISFET and pMISFET while maintaining the same current direction, eliminating area penalties and circuit design complexities, thus enabling a high-performance, low-power CMOS structure.
Implementation Method 1
an Si layer having a uniaxial tensile strain in a channel length direction
Implementation Method 2
an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction
Implementation Method 3
a manufacturing method involving epitaxial growth and oxidation to achieve these strains
Implementation Method 4
a manufacturing method involving epitaxial growth and oxidation to achieve these strains
Data Source
AI summary
A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a <110> direction.