Strained Source/Drain SiGe Profile to Limit Dislocation Growth
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling integrated chip components due to limitations in transistor performance enhancement, where traditional strain engineering methods may lead to dislocation formation and reduced strain benefits, especially at advanced technology nodes.
Innovation Solution
A strained channel transistor device is developed with a discontinuous germanium concentration profile in the source and drain regions, using multiple epitaxial layers of silicon germanium (SiGe) with varying germanium concentrations to induce strain on the channel region, thereby enhancing mobility and reducing dislocation propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If continuous germanium concentration profile is used in source/drain regions, then strain benefits are improved, but dislocation formation increases
Solution Approach 1:
The source/drain region is divided into multiple epitaxial layers with different germanium concentrations. The structure includes a first epitaxial layer with higher germanium concentration and a second epitaxial layer with lower germanium concentration, creating a segmented concentration profile that reduces dislocation while maintaining strain
Solution Approach 2:
Different regions of the source/drain structure are assigned different germanium concentrations tailored to their specific functions. The higher germanium concentration is placed in regions requiring maximum strain, while lower concentration regions are positioned to minimize dislocation propagation, creating localized optimization throughout the structure
2Speed
If germanium concentration is increased to enhance strain, then mobility improvement is achieved, but dislocation propagation is reduced
Solution Approach 1:
The germanium concentration is varied in the vertical dimension through multiple epitaxial layers rather than being uniform throughout. This dimensional approach allows high germanium concentration to provide strain for mobility enhancement while the layered structure interrupts dislocation propagation paths in the vertical direction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves transistor performance by maintaining strain benefits while minimizing dislocation issues, allowing for more efficient scaling of integrated chip designs and performance enhancement at advanced technology nodes.
Implementation Method 1
Strain engineering is often utilized to improve the performance of transistor devices. For example, by inducing a compressive stress onto a channel region of a PMOS transistor, the mobility and performance of the transistor is improved.
Implementation Method 2
A strained channel transistor device is developed with a discontinuous germanium concentration profile in the source and drain regions, using multiple epitaxial layers of silicon germanium (SiGe) with varying germanium concentrations to induce strain on the channel region, thereby enhancing mobility and reducing dislocation propagation.
Data Source
AI summary
The present disclosure relates to a method of forming a transistor device. The method may be performed by forming a gate structure onto a semiconductor substrate and forming a source/drain recess within the semiconductor substrate adjacent to a side of the gate structure. One or more strain inducing materials are formed within the source/drain recess. The one or more strain inducing materials include a strain inducing component with a strain inducing component concentration profile that continuously decreases from a bottommost surface of the one or more strain inducing materials to a position above the bottommost surface. The bottommost surface contacts the semiconductor substrate.