Strained SiGe Fin Channels With Isothermal Epitaxy
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Solution Overview
Problem
Traditional FinFET manufacturing faces challenges in achieving high performance due to tight gate dimensions and complex doping and strain engineering, particularly in scaling down device size.
Innovation Solution
The method involves forming p-channel and n-channel fins on the same substrate using different semiconductor materials, with p-channel fins made of silicon germanium alloy grown through an isothermal epitaxial process, ensuring uniform thickness and reduced defects, which enhances mobility and simplifies subsequent fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional FinFET manufacturing processes are used with tight gate dimensions, then device scaling is achieved, but doping and strain engineering become very challenging
Solution Approach 1:
The patent changes the material parameter by introducing silicon germanium alloy with different germanium concentrations (e.g., 5-15% Ge for n-channel, 15-30% Ge for p-channel) to achieve strain engineering without relying on traditional doping processes. This material composition change enables performance improvement in scaled devices where conventional doping becomes difficult
Solution Approach 2:
The patent uses composite semiconductor materials consisting of silicon and germanium in specific ratios to create strained channel regions. The silicon germanium alloy layers are deposited on silicon substrates to form heterostructures that provide both mechanical strain and electrical performance benefits in tightly-scaled FinFET devices
2Manufacturing precision
If isothermal epitaxial process is used for growing silicon germanium alloy, then uniform thickness and reduced defects are achieved, but process complexity increases
Solution Approach 1:
The patent applies isothermal processing conditions where the epitaxial growth is performed at a constant temperature throughout the process. This equipotential thermal field ensures uniform deposition rate and thickness across the wafer surface, reducing thickness variation and defects while maintaining process control
3Reliability
If different semiconductor materials are used for p-channel and n-channel fins, then charge carrier mobility is enhanced, but fabrication process complexity increases
Solution Approach 1:
The patent applies different silicon germanium alloy compositions to different regions: n-channel fins use lower germanium concentration (5-15%) while p-channel fins use higher germanium concentration (15-30%). This local material optimization enhances charge carrier mobility specifically where needed for each transistor type without requiring completely separate fabrication lines
Solution Approach 2:
The patent segments the semiconductor structure into distinct n-channel and p-channel fin regions with different material compositions. By dividing the device into functionally-separated regions with optimized materials for each, the patent achieves high mobility for both transistor types while using a unified epitaxial growth process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of p-type FinFETs by enhancing charge carrier mobility and reduces fabrication time and defects, leading to more uniform and efficient manufacturing of FinFET devices.
Implementation Method 1
epitaxially growing a second layer having silicon germanium (SiGe) over the first portion of the first layer
Data Source
AI summary
A method includes forming an N well and a P well in a substrate; depositing a first layer having silicon over the N well and the P well; depositing a first dielectric layer over the first layer; forming a resist pattern over the first dielectric layer, the resist pattern providing an opening directly above the N well; etching the first dielectric layer and the first layer through the opening, leaving a first portion of the first layer over the N well; removing the resist pattern; and epitaxially growing a second layer having silicon germanium (SiGe) over the first portion of the first layer. The epitaxially growing the second layer includes steps of (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a SiGe layer over the silicon seed layer, wherein the steps (a), (b), and (c) are performed under about a same temperature.