Strained SiGe Fin Channel Growth With Defect-Control Seed Layers
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Solution Overview
Problem
Fully strained channels in CMOS devices are prone to epitaxial growth defects and structural deformations due to processing stress, which can offset mobility benefits, particularly in p-type field effect transistors with larger Si to SiGe lattice mismatch.
Innovation Solution
A fabrication method involving multiple surface pre-clean treatment cycles with nitrogen trifluoride and ammonia plasma, followed by thermal treatment, and epitaxial growth with a Si seed layer or SiGe seed layer, is used to mitigate defects and deformations, ensuring a substantially defect-free and vertically oriented SiGe channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epitaxial growth is performed to form SiGe channel region, then carrier mobility is improved and drive current enhancement is achieved, but epitaxial growth defects and structural deformations occur due to processing stress and lattice mismatch
Solution Approach 1:
Surface pre-clean treatment cycles are performed before epitaxial growth to prepare the substrate surface, removing contaminants and oxides that could cause defects during subsequent growth processes
Solution Approach 2:
Thermal treatment is applied to mitigate processing stress and prevent structural deformations before they occur during epitaxial growth, counteracting the harmful effects of lattice mismatch between Si and SiGe
2Manufacturing precision
If multiple surface pre-clean treatment cycles and thermal treatment are applied, then epitaxial growth defects are reduced, but fabrication process complexity increases
Solution Approach 1:
The surface preparation process is divided into multiple discrete pre-clean treatment cycles, each targeting specific types of contaminants, allowing systematic control of surface quality without overwhelming complexity
Solution Approach 2:
The thermal treatment step serves multiple functions simultaneously: it performs annealing to reduce stress, prepares the surface for epitaxial growth, and mitigates lattice mismatch effects, consolidating several functions into one process step
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces epitaxial growth defects and structural deformations, maintaining strain-induced drive current enhancement and carrier mobility improvements in CMOS devices, particularly for p-type transistors, while ensuring the integrity of the channel region.
Implementation Method 1
multiple surface pre-clean treatment cycles with nitrogen trifluoride and ammonia plasma
Implementation Method 2
multiple surface pre-clean treatment cycles with nitrogen trifluoride and ammonia plasma
Implementation Method 3
followed by thermal treatment
Implementation Method 4
epitaxial growth with a Si seed layer or SiGe seed layer
Data Source
AI summary
The present disclosure describes an exemplary fin structure formed on a substrate. The disclosed fin structure comprises an n-type doped region formed on a top portion of the substrate, a silicon epitaxial layer on the n-type doped region, and an epitaxial stack on the silicon epitaxial layer, wherein the epitaxial stack comprises a silicon-based seed layer in physical contact with the silicon epitaxial layer. The fin structure can further comprise a liner surrounding the n-type doped region, and a dielectric surrounding the liner.