Strained SiGe FinFET with Silicon Pedestals for Strain Retention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current SiGe FinFETs face strain relaxation issues, particularly at the end portions of the fins, which hampers performance due to the difficulty in maintaining strain as the fins are cut to desired lengths, limiting further scaling and performance enhancement.
Innovation Solution
A semiconductor structure featuring a strained silicon germanium alloy fin with silicon pedestals and a gate spacer that fills an undercut region beneath raised source/drain structures, maintaining strain and improving overlay capacitance, and a method for forming this structure involving sacrificial gate removal and epitaxial growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If SiGe fins are cut to desired length, then device dimensions are reduced and scaling is achieved, but strain relaxation occurs especially at end portions of the fins
Solution Approach 1:
Silicon pedestals are formed on the substrate before the SiGe fins are grown. These pedestals remain after sacrificial material removal and serve to maintain strain in the SiGe fins by providing a strained silicon germanium interface that prevents strain relaxation at the fin ends.
Solution Approach 2:
The silicon pedestals act as intermediary structures between the substrate and the SiGe fins. They mediate the strain maintenance function by providing a compliant interface that preserves the strained state of the SiGe channel material even after the fins are cut to desired lengths.
2Reliability
If gate spacer lower portion fills undercut region beneath raised source/drain structures, then overlay capacitance is improved, but device structure complexity increases
Solution Approach 1:
The gate spacer is formed with a lower portion that extends into the undercut region beneath the raised source/drain structures, utilizing the vertical dimension to improve overlay capacitance. This three-dimensional configuration allows the gate spacer to provide capacitive coupling without increasing lateral device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively maintains strain in SiGe fins, enhancing the performance of FinFET devices by improving overlay capacitance and maintaining the integrity of the strained channel material, thus overcoming the limitations of strain relaxation in current SiGe FinFETs.
Implementation Method 1
the SiGe fins suffer from strain relaxation do to cutting the SiGe fins to a desired length. In such instances, the strain relaxes, especially at the end portions of the SiGe fins.
Implementation Method 2
a strained silicon germanium alloy fin with silicon pedestals and a gate spacer that fills an undercut region beneath raised source/drain structures
Data Source
AI summary
A semiconductor structure is provided including a strained silicon germanium alloy fin that can be employed as a channel material for a FinFET device and having a gate spacer including a lower portion that fills in a undercut region that lies adjacent to the strained silicon germanium alloy fin and beneath raised source/drain (S/D) structures and silicon pedestal structures that can provide improved overlay capacitance.