Strained SiGe FinFET Gate Stack CETinv Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Achieving aggressive gate length with tightly contacted gate pitches in FinFET devices is hindered by the difficulty in obtaining a desired level of interface passivation for Ge content in Si1-xGex, resulting in high equivalent inversion capacitance oxide thickness (CETinv) levels.
Innovation Solution
The method involves providing a substrate with strained SiGe and Si layers, defining fins in each, depositing a thin layer of Ge, forming a gate dielectric, and using a high dielectric constant gate stack to scale down CETinv, with the Ge content in Si1-xGex ranging from 0.4 to 0.6 for pFETs and using s-Si or Group III-V materials for nFETs, along with an ultra-thin strained-Ge cap layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If Ge content in Si1-xGex is increased to achieve aggressive gate length scaling, then gate length can be reduced, but interface passivation quality deteriorates resulting in high CETinv levels
Solution Approach 1:
The patent segments the fin structure into multiple functional layers: strained SiGe layer for channel formation, ultra-thin Ge cap layer (1-3 monolayers) for interface passivation enhancement, and relaxed SiGe buffer layer for strain management. This segmentation allows each layer to optimize its specific function, resolving the contradiction between aggressive scaling and interface quality.
Solution Approach 2:
The patent applies local quality by placing Ge atoms specifically at the surface interface (cap layer) where passivation is needed, rather than uniformly distributing Ge throughout the entire fin structure. The ultra-thin Ge cap layer provides localized interface passivation enhancement exactly where required, maintaining high CETinv performance while enabling aggressive gate scaling.
2Manufacturing precision
If ultra-thin Ge cap layer is deposited to enhance interface passivation, then CETinv is reduced, but manufacturing complexity increases
Solution Approach 1:
The relaxed SiGe buffer layer acts as an intermediary between the strained SiGe channel layer and the Ge cap layer. It manages the complex strain relationships and lattice mismatches, enabling the deposition of the ultra-thin Ge cap layer without requiring excessively complex manufacturing processes. The buffer layer mediates the strain transfer, simplifying the overall fabrication complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively scales down CETinv to 0.8 nm-0.9 nm, enhancing Ge content and enabling aggressive gate length scaling without affecting the interface, while maintaining electron mobility.
Implementation Method 1
the charge carrier mobility is theoretically adequate with a reasonable strain, which can be achieved by growing the Si1-xGex material on a strain relaxed buffer (SRB) or on strained Si direct on insulator (SSDOI)
Implementation Method 2
the equivalent inversion capacitance oxide thickness (CETinv or Tinv) becomes an important consideration
Data Source
AI summary
A structure includes a substrate; a plurality of pFET fins disposed over the substrate; and a plurality of nFET fins disposed over the substrate. In the structure each of the plurality of pFET fins is composed of s-Si1-xGex, where x has a value in a range of about 0.4-0.6; each of the plurality of nFET fins is composed of one of s-Si or a Group III-V material; and each of the plurality of pFET fins and the plurality of nFET fins includes a thin (e.g., <1 nm) multilayer structure containing a plurality s-Ge monolayers disposed on a surface thereof, a gate dielectric disposed over the multilayer structure, and a gate conductor disposed over the gate dielectric. The presence of the multilayer structure containing the plurality s-Ge monolayers enhances Tinv scaling by effectively increasing a Ge percentage of the s-Si1-xGex pFETs. Methods to fabricate the structure are also disclosed.