Strained SiGe FinFET Fabrication via Selective Etching
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Solution Overview
Problem
Current semiconductor devices face challenges in enhancing carrier mobility for both n-type and p-type fins in CMOS technology, as Germanium used for p-type fins can reduce electron mobility in n-type fins, and achieving strained cladding layers without relaxed substrates is complex and costly.
Innovation Solution
The use of a (110) surface wafer with initially strained SiGe fins and a silicon cladding layer for n-type fins, and a different cladding structure for p-type fins, including a SiGe core and outer Si cladding layer, to achieve high electron and hole transport without relaxed substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If strained cladding layers are formed without relaxed substrates to simplify manufacturing, then process complexity is reduced, but achieving proper strain and lattice matching becomes difficult
Solution Approach 1:
The patent changes the material composition parameter by using pure silicon for n-type fins instead of SiGe, which has a lattice constant closer to silicon. This parameter change allows the formation of strained cladding layers without relaxed substrates while maintaining proper lattice matching, as the smaller lattice mismatch enables direct epitaxial growth of strained silicon cladding layers on the n-type fins without requiring substrate relaxation processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high carrier mobility and drive currents for both n-type and p-type transistors, improving performance and reducing energy consumption by overcoming the limitations of traditional substrate relaxation methods.
Implementation Method 1
The cladding layer may be strained, and the strained cladding layer may improve mobility of carriers in the channel flow direction
Implementation Method 2
Both the p-type and n-type fins may comprise an upper portion that is substantially uniformly SiGe
Data Source
AI summary
Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.