Strained SiGe Layer Lattice Parameter Gradient
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Solution Overview
Problem
In semiconductor manufacturing, the high Ge-content in strained SiGe layers for MOS transistors leads to defects at the SiGe-substrate interface due to significant differences in lattice parameters, and Ge atoms can degrade the quality of metal silicide layers during the salicide process.
Innovation Solution
A semiconductor structure with a doped strained layer having a non-uniform lattice parameter distribution is fabricated using an epitaxy process where the percentage of a non-silicon IV-group element gas is increased over time, reducing lattice parameter differences between the strained layer and the substrate, and a silicon layer is formed before the metal silicide layer to prevent Ge atoms from entering it.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high Ge-content strained SiGe layer is used to increase compressive stress and carrier mobility, then device speed is improved, but defects occur at the SiGe-substrate interface due to large lattice parameter difference
Solution Approach 1:
The patent applies local quality by creating a strained SiGe layer with non-uniform Ge-content distribution. The Ge-content is higher near the substrate interface and decreases toward the top surface, allowing the bottom region to provide strong compressive stress for high carrier mobility while the top region maintains better lattice matching to reduce interface defects
Solution Approach 2:
The patent changes the lattice parameter distribution within the strained SiGe layer by varying Ge-content through the layer thickness. This parameter change creates a gradient structure where the lattice parameter transitions from a large mismatch at the interface to a smaller mismatch at the surface, resolving the contradiction between stress generation and defect prevention
2Speed
If high Ge-content strained SiGe layer is used to increase compressive stress, then device speed is improved, but Ge atoms enter the metal silicide layer during salicide process degrading its quality
Solution Approach 1:
The patent applies local quality by concentrating the Ge-content variation in the lower portion of the strained SiGe layer. The high Ge-content region is localized near the substrate where it provides compressive stress, while the upper region has lower Ge-content, reducing Ge atom diffusion into the metal silicide layer during the salicide process
Solution Approach 2:
The patent performs preliminary action by forming the strained SiGe layer with controlled Ge-content distribution before the salicide process. This pre-configuration of the Ge-content gradient prevents excessive Ge atom diffusion into the metal silicide layer during subsequent processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decreases defects at the interface and maintains the quality of the metal silicide layer by minimizing lattice parameter differences and isolating Ge atoms from the silicide process.
Implementation Method 1
a doped strained layer 112 is formed in the opening 110
Data Source
AI summary
A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor is disposed on the second well, including a gate structure on the second well and a strained layer of the first conductivity type in an opening in the second well beside the gate structure. The difference between the cell parameter of a portion of the strained layer near the bottom of the opening and that of the substrate is less than the difference between the cell parameter of a portion of the strained layer apart from the bottom of the opening and that of the substrate. The second MOS transistor is disposed on the first well.