Strained SiGe p-FET Channel via Epitaxial Diffusion
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Solution Overview
Problem
Current methods for forming p-type field effect transistor (p-FET) devices with strained silicon-germanium channels alter the dimensions of the channel region, affecting the performance and reliability of fully depleted CMOS FET devices, as p-FET and n-FET devices in integrated circuits often have varying channel dimensions.
Innovation Solution
A method is developed to form p-FET devices with a strained silicon-germanium channel of unvarying dimensions by epitaxially growing a silicon-germanium layer above the source-drain region, followed by thermal annealing to diffuse germanium atoms into the channel region, ensuring a homogeneous distribution without altering the channel dimensions, and forming a doped epitaxial layer to create a raised source-drain region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional methods are used to form p-FET devices with strained silicon-germanium channels, then hole mobility is enhanced, but the channel region dimensions are altered, affecting device performance and reliability
Solution Approach 1:
The channel region is divided into two distinct zones: a strained silicon-germanium channel region with enhanced hole mobility and an unstrained silicon channel region that maintains dimensional consistency. This segmentation allows each region to fulfill its specific function without compromising the other, resolving the contradiction between mobility enhancement and dimensional precision.
Solution Approach 2:
Strain is applied locally to only the portion of the channel region where it is needed for mobility enhancement, while the rest of the channel maintains its original dimensions and properties. This localized approach to strain engineering allows mobility improvement without altering the overall channel dimensions that are critical for device matching.
2Reliability
If the channel dimensions are maintained consistent between p-FET and n-FET devices, then device matching and reliability are improved, but hole mobility enhancement through strain is reduced
Solution Approach 1:
The channel is segmented into strained and unstrained regions, where the strained portion provides mobility enhancement and the unstrained portion maintains dimensional consistency with n-FET devices. This enables both device matching and mobility improvement to coexist.
Solution Approach 2:
The crystal structure parameters (strain state) are changed locally in the channel region without altering the geometric dimensions. By modifying the strain parameter rather than the dimensional parameters, hole mobility is enhanced while maintaining consistent channel dimensions for device matching.
3Reliability
If germanium atoms are diffused into the channel region to enhance hole mobility, then device performance is improved, but the distribution uniformity and channel dimensions may be compromised
Solution Approach 1:
A silicon-germanium layer is formed above the source-drain region before the channel region during epitaxial growth. This preliminary positioning of germanium atoms allows controlled diffusion into the channel region during subsequent thermal processing, achieving uniform distribution without compromising channel dimensions.
Solution Approach 2:
The silicon-germanium layer formed above the source-drain region serves as an intermediary reservoir that supplies germanium atoms to the channel region during thermal diffusion. This intermediary structure enables controlled and uniform germanium distribution in the channel without direct manipulation, preserving both composition stability and dimensional integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances hole mobility and improves device performance by maintaining consistent channel dimensions between p-FET and n-FET devices, effectively controlling the short-channel effect and enhancing the overall performance of CMOS FET devices.
Implementation Method 1
A silicon-germanium layer may be epitaxially grown above the source-drain region
Implementation Method 2
The semiconductor structure may be annealed to diffuse germanium atoms from the silicon-germanium layer into the channel region
Implementation Method 3
The semiconductor structure may be annealed to diffuse germanium atoms
Implementation Method 4
p-FET devices with a strained silicon-germanium channel
Data Source
AI summary
A method of forming a semiconductor structure includes forming a dummy gate above a semiconductor substrate. The dummy gate defines a source-drain region adjacent to the dummy gate and a channel region below the dummy gate. A silicon-germanium layer is epitaxially grown above the source-drain region with a target concentration of germanium atoms. The semiconductor structure is annealed to diffuse the germanium atoms from the silicon-germanium layer into the channel region to form a silicon-germanium channel region.